Pulse Triggered (Level Triggered or Gated) SR Flip Flop (Latch)

Summary

This video explains the working of a pulse-triggered SR flip-flop, also known as a gated SR flip-flop or SR latch. It discusses how the output responds to input changes at specific levels of the enable signal (positive or negative), and illustrates the behavior of the SR latch with a circuit diagram, truth table, and waveform analysis. The video emphasizes the differences between positive and negative level triggering and concludes with the characteristic equation for an SR latch. The next video promises to explore edge-triggered SR flip-flops, highlighting the contrast between level and edge triggering.

Takeaways

• ⚡ Pulse-triggered flip-flops, also known as level-triggered or gated flip-flops/latches, respond to input changes at a specific level of the enable signal.
• 🔌 The SR flip-flop has two main inputs, S (set) and R (reset), along with an enable input (E or G) that controls when the flip-flop is active.
• 🟢 When the enable input is at a positive level, the flip-flop becomes active and reacts to changes in S and R inputs.
• 🔴 If the enable input is zero, the flip-flop ignores changes in S and R, maintaining its current state.
• 🧮 The truth table shows that the SR flip-flop's next state depends on both S and R inputs and the enable signal, determining whether the flip-flop sets, resets, or holds its value.
• 📝 A flip-flop is considered 'set' when S = 1, R = 0, and the output becomes 1, and it is 'reset' when S = 0, R = 1, making the output 0.
• ⛔ When both S and R are 1, the flip-flop state is indeterminate, meaning the output is undefined.
• 🔄 The characteristic equation of the SR latch describes the relationship between present state, next state, and the S and R inputs, forming the basis for predicting its behavior.
• 🌊 The behavior of the gated SR latch can be visualized with timing diagrams that show how the output responds to changes in enable, set, and reset signals over time.
• 🔄 The flip-flop behaves differently under negative level triggering, where it becomes active when the enable input is 0, instead of 1.

Q & A

What is a pulse-triggered SR flip flop?

A pulse-triggered SR flip flop, also known as a level-triggered or gated SR flip flop, responds to input changes only when there is a positive or negative level on the enable input. The enable input can be referred to as the gate signal, and it controls when the flip flop is active.

What are the inputs of a pulse-triggered SR flip flop?

The inputs of a pulse-triggered SR flip flop include the Set (S), Reset (R), and Enable (EN) or Gate (G) signals. The flip flop's output depends on the state of these inputs, particularly when the enable signal is at an active level.

What happens when the enable input is 0 in a pulse-triggered SR flip flop?

When the enable input is 0, the output of the flip flop remains unchanged, regardless of the values of the Set (S) and Reset (R) inputs. The output will follow the previous state.

What is the significance of a positive level-triggered flip flop?

In a positive level-triggered flip flop, the flip flop only responds to input changes when the enable input is at a positive (high) level. This makes the flip flop active and able to produce output based on the current inputs.

What is the output of a flip flop when S = 0, R = 1, and the enable signal is 1?

When S = 0, R = 1, and the enable signal is 1, the flip flop will reset, meaning the next state of the output will be 0, indicating the reset state.

What is the output when both S and R are 1 in a pulse-triggered SR flip flop?

When both S and R are 1 in a pulse-triggered SR flip flop, the output becomes indeterminate or undefined. This is typically avoided in practical use since the flip flop does not produce a clear output in this state.

How does the gated SR flip flop work in relation to enable input timing?

The gated SR flip flop only responds to input changes when the enable input is 1 (positive level). If the enable input is 0, the flip flop holds its current output. The waveform of the enable signal controls when the flip flop can update its output based on the Set and Reset inputs.

What is the difference between a positive level-triggered and a negative level-triggered SR flip flop?

A positive level-triggered SR flip flop responds to inputs when the enable signal is at a positive (high) level, while a negative level-triggered SR flip flop only responds when the enable signal is at a negative (low) level. The behavior of the flip flop changes based on the level of the enable input.

What does the characteristic equation of an SR flip flop represent?

The characteristic equation of an SR flip flop defines the relationship between the next state of the flip flop (Qn+1), the current state (Qn), and the Set (S) and Reset (R) inputs. It is a formula that helps predict the output of the flip flop based on its inputs and current state.

What is the purpose of using a gated SR latch instead of a regular SR latch?

A gated SR latch includes an additional enable input that controls when the latch can respond to changes in the Set and Reset inputs. This allows for more controlled operation, as the latch only updates its output when the enable signal is active, making it more suitable for synchronous circuits.

Outlines

00:00

🔄 Introduction to Pulse-Triggered SR Flip-Flop

This paragraph introduces the concept of a Pulse-Triggered SR Flip-Flop, also known as a Level-Triggered or Gated SR Flip-Flop/Latch. It explains that the flip-flop's output responds to the level of the enable input, which acts as a gate. The flip-flop has two inputs, S (set) and R (reset), and an additional enable or gate input. The behavior of the flip-flop is dependent on the level of the enable input, whether positive or negative. The paragraph also mentions that the flip-flop can be represented as a latch by default but can also be considered as a flip-flop. It concludes by stating that a detailed explanation with a circuit diagram will follow.

05:00

📈 Understanding the Operation of SR Flip-Flop with Truth Table

This paragraph delves into the operational details of the SR flip-flop with an emphasis on its truth table. It explains how the flip-flop's output changes based on the inputs S and R, and the level of the enable input. The truth table provided shows the current output (q) and the next output (q+1) of the flip-flop after the enable signal is applied. The paragraph also discusses the concept of positive and negative level triggering, where the flip-flop responds to either the positive or negative level of the enable input. The behavior of the flip-flop is further clarified with examples of how the flip-flop remains unchanged unless the enable input is active (high or low depending on the type).

10:02

📊 Waveform Analysis of Gated SR Latch

In this paragraph, the operation of the gated SR latch is explained through waveform analysis. It describes how the flip-flop's output (Q and Q Bar) changes in response to the set (S), reset (R), and enable inputs over time. The paragraph illustrates the flip-flop's behavior when the enable signal is high and when it is low, showing how the flip-flop sets or resets accordingly. The waveforms are used to demonstrate the flip-flop's response to different input combinations, including the indeterminate state when both S and R are high.

15:03

🔢 Deriving the Characteristic Equation of SR Latch

The final paragraph focuses on deriving the characteristic equation of the SR latch. It explains that the characteristic equation represents the relationship between the next state of the flip-flop, its present state, and the inputs. The paragraph walks through the process of simplifying the truth table to form the equation, which is expressed as q(n+1) = S + R'q(n). This equation captures the essence of how the flip-flop's next state is determined by the current state and inputs when the enable signal is active. The paragraph also briefly touches on the difference between positive and negative level triggering in SR flip-flops.

Keywords

💡Pulse Triggered

Pulse triggered refers to a flip-flop or latch that changes its output only when a certain level of the enable input is reached, either positive or negative. In the context of the video, the SR flip-flop is considered pulse triggered when the output responds to the input changes at a specific level of the enable input.

💡SR Flip-Flop

An SR flip-flop is a type of bistable circuit with two inputs: Set (S) and Reset (R). It stores binary data and changes state based on the values of S and R. In the video, the SR flip-flop's operation is explained with positive and negative level triggering, where the output changes according to the S and R inputs when the enable signal is activated.

💡Latch

A latch is a circuit that holds its output constant unless acted upon by an input signal. The video refers to the SR flip-flop as a latch when the output responds to the enable signal at a certain level. It is often called a gated SR latch when combined with enable signals.

💡Enable Input

The enable input (EN) controls whether the flip-flop or latch is active. In the video, the enable input dictates when the SR flip-flop responds to changes in the S and R inputs. Only when the enable input is set to a certain level, either positive or negative, does the flip-flop change state.

💡Positive Level Triggered

Positive level triggered refers to a flip-flop that changes its output only when the enable input is high (positive). In the video, this is explained in the context of the SR flip-flop, where it only responds to input changes when the enable signal is at a positive level.

💡Negative Level Triggered

Negative level triggered flip-flops change their output only when the enable input is low (negative). In the video, this concept is illustrated by showing how the SR flip-flop behaves when the enable signal is at a low level, causing the flip-flop to respond only during this period.

💡Truth Table

A truth table represents all possible input combinations and the corresponding outputs for a digital circuit. In the video, the truth table of the SR flip-flop is explained to show how different combinations of the S, R, and enable inputs affect the next state of the flip-flop.

💡Set

Set (S) is one of the inputs of the SR flip-flop that controls when the output should be 'set' to 1. In the video, the set condition is explained as part of the truth table, where the flip-flop is set when S is 1 and R is 0, making the output high.

💡Reset

Reset (R) is the input of the SR flip-flop that resets the output to 0. In the video, this input is explained in the context of how the flip-flop goes into a reset state when R is 1 and S is 0, making the output low.

💡Indeterminate State

Indeterminate state refers to the condition in an SR flip-flop when both inputs (S and R) are set to 1, leading to an undefined output. In the video, this situation is referred to as a case where the flip-flop output cannot be reliably determined and is marked as 'not defined' or indeterminate in the truth table.

Highlights

Pulse-triggered SR flip-flop or latch is also known as level-triggered or gated SR flip-flop or latch.

The flip-flop's output responds to input changes only at the positive or negative level of the enable input.

Enable input, also known as gate input, determines the flip-flop's response to input changes.

The SR flip-flop has two inputs, S (set) and R (reset), and an enable or gate input.

The flip-flop's output depends on the level of the enable input or gate signal.

If the output responds to the positive level of the enable input, it is known as positive level-triggered flip-flop or latch.

If the output responds to the negative level of the enable input, it is known as negative level-triggered flip-flop or latch.

The block diagram representation of the SR latch is explained with a gated SR latch.

The SR latch has NAND gates in its circuit.

The truth table of the SR latch is detailed, showing the relationship between present and next outputs.

The flip-flop's output remains unchanged as long as the enable input is zero.

The flip-flop is active only when the enable input is one in positive level-triggered flip-flops.

The flip-flop will reset if S is 0 and R is 1, regardless of the enable input.

The flip-flop will set if S is 1 and R is 0, with the enable input active.

The state of the flip-flop is indeterminate if both S and R are 1.

Waveform analysis demonstrates the flip-flop's response to changes in S, R, and enable inputs over time.

The characteristic equation of the SR latch is derived, relating the next state to the present state and inputs.

The negative level-triggered SR flip-flop is symbolized with a circle indicating negative triggering.

In negative level-triggered flip-flops, the flip-flop is active when the enable signal is zero.

Transcripts

in this video I will discuss about pulse

triggered Sr flip flop or latch so pulse

triggered is also known as level

triggered or also known as gated Sr flip

flop or srf latch so here the name flip

flop

or latch so when there is a pulse

triggering or the level triggering by

default it will be latch but we can also

represent it as flip flop

impulse triggered flip flop output of

the flip flop response to the input

changes only at positive or negative

level of the enable input here the

enable in enable input is nothing but

gate input so sometimes it is also known

as gated flip flop or gated latch so in

Sr flip

so in first triggered Sr flip flop we

have two inputs that is s and r

along with that we have one more input

represented as either by E which

represent enable signal or by G which

represent get signal so here the output

is not only dependent on S standard it

is also dependent on either positive or

negative level of the enable input or

gate signal

if output of the flip flop responds to

the input changes only at positive level

of the enable input then it is known as

positive level triggered flip flop or

latch

similarly if output of the flip flop

responds to the input changes only at

negative level of the enable input then

it is known as negative level triggered

flip flop or latch

now let me explain this in detail with

circuit diagram

so this is the block diagram

representation of Sr latch that is gated

SRH or pulse triggered Sr latch now let

me write it as

R latch

so here we have two inputs that is one

input is s s represents set and R which

is nothing but reset

so here this is the enable input I will

represent it as say en so in place of En

we can also use g g for gate it has two

outputs one is

Q output another output is q1 which is

complement of this Q output

so here this is the circuit of Sr latch

with nand Gates so here this is s input

that is set and we have r that is this

is our input and this one is nothing but

enable input it has two output that is q

and Q Bar so this is Q output and this

will be Q Bar output

so in my Sr Latch video I have clearly

explained how this Sr latch will work

now directly I will write this truth

table

that is

so here en stands for enable input SC

set R is reset q n q n stands for

present output q n plus 1 stands for

next output

the difference between present output

and next output is after applying the

enable signal

the flip flop produce the output that

we'll call it as next output and this

state indicates the status of the flip

flop so in

pulse triggered flip flop as long as

enable input is zero that is if enable

input is zero

irrespective of S and R that is s may be

0 or 1 that is do not care R may be 0 or

1

suppose the present state of the flip

flop is zero

so when enable is 0 the next state of

the flip flop will be zero

similarly if enable input is zero

irrespective of S and R that is s may be

0 or 1 or maybe 0 or 1 suppose the

present state of the flip flop is one in

that case also the next state is same as

the present state that is next state is

same as present State now here we can

say the status of the flip flop as there

is no change in the output that is

present State and next state outputs are

same we can call it as no change

there is no change in the output so here

also there is no change in the output as

I said here we'll consider positive

level triggered so let me let e n is

positive level triggered in that case

when e n is 1 then only flip flop will

be active that is if n is 1

so in all other cases I will consider e

n as 1

so if S and R are

s is 0 and R is 0

that is SC 0 R is 0 suppose present

state of the flip flop is 0 in that case

if s is 0 R is 0 the next state of the

flip flop is

same as present State there is no change

similarly

for S is 0 and R is 0 suppose q n that

is present state is 1 in that case also

next state will be same as present state

so here also there is no change

here also we have

no change

so now let me consider

suppose yes input is 0

R input is 1

if q n there is present state of the

flip flop is 0 in that case here we can

see that s c is 0 that is set equal to 0

and reset is equal to 1 in that case the

flip flop will reset that is next state

of the flip flop is reset reset means

zero the status or state is reset the

flip flop will be in reset state that is

if s is 0 and R is 1 flip flop is reset

means 2N plus 1 is 0 or Q is 0.

similarly

the same thing that is s is 0 and

R is 1 but present state of the flip

flop is say one in that case as I said

here s is 0 R is 1 means it is flip flop

is reset the present state q n is equal

to 1 it indicates that flip flop is in a

set state that is Q equal to 1 means

flip flop is in set state

so the next state of the flip flop will

be zero

so when s is 0 R is 1 when reset is one

flip flop will reset so flip flop is

reset means output is zero here also it

is reset

similarly

suppose s is 1

and R is 0 so flip flop will set

so here s is 1 R is 0 R is 0 and enable

input is one therefore the flip flop

will set so it will be set similarly for

the same state that is let me consider s

equal to 1 r equal to 0 suppose flip

flop is in

set state that is 1 so in that case

when s c is 1 R is 0 suppose the flip

flop is in set state it will follow the

same state in the next state when that

is one itself so here also it is set

suppose s is 1 and R is 1

q n is 0

so in Sr flip flop if S and R are one

that is if both the inputs are 1

and if 2 N is 0 there is present state

of the flip flop is 0 then q n plus 1

will be not defined in both the cases it

will be not defined

we'll call it as indeterminate

here also it is indeterminate

now let me explain the working of this

flip flop that is gated Sr latch with

waveform

so I will consider this signal as set

signal that is s

I will call this signal as set

I will call this signal as say reset

and let me take this as enable input say

this is enable input or gate input so

here we can observe that from here to

here it is 0 enable signal is zero

from here to here it is 1 and from here

to here it is again 0 and from this

period to this period its value is 1

after that its value is 0.

so this is with respect to time

so let me take this as Q output

that is output of the Flip Flop and let

me take this as

Q Bar because flip flop has two outputs

q and Q Bar both are complement of each

other so here

as I said according to according to this

truth table when enable input is 0 flip

flop there is no change in the flip flop

so here that we can observe here

so from this period to this period the

enable signal is zero at in this period

the value of that is

I can show here from here to here the

value of s is 0 here the value of R is 0

that is when s is 0 or R is 0 that is

irrespective of this the flip flop will

follow the same previous value that is q

n plus 1 is same as q n it means that it

will follow

the previous value that is the if we

assume the previous value as 0 the flip

flop will become 0 itself

so from till this period its value will

be 0

so now from here to here that is from

here to here the value of s is 0 value

of R is 0 but enable signal is one here

we can see that enable signal is one so

when enable is 1 s is 0 and R is zero

you both s is 0 and R is 0 there is no

change so no change means the flip flop

will carry the previous value the

previous value was 0 the same thing will

continue so from here to here the same

thing will continue

so now at this moment we can see that s

value is 1 from here to here this value

is 1 but here the R value is 0 the flip

flop is in

enable equal to 1. so here we can see

that s is one R is 0.

so into table we can see s is one R is 0

flip flop will be in set state

here also we can see enable is 1. so

that the flip flop will become set set

means one the flip flop will go higher

output will be high so till from here to

here the output is high

so from here to here I can show here

here to here the output is high

so now from this point to this point s

is 0 and R is 0 when s is 0 and R is 0

and enable is 1 here also enable is one

we can see that s is 0 R is 0 enable is

one there is no change

because there is no change means if the

previous output was Zero the same thing

will be followed if it is 1 same thing

will be followed so here we can see that

the previous one was one

previous output was one same thing will

be carried so it will be 1 itself so

till this point its value is 1.

so at this moment we can see that R is

equal to 1 here but s is equal to zero

so when s is 0 R is 1 here we can see

that enable is one that is when s is 0 R

is 1 and enable is 1

if flip flop is in previous state is 1

it will become 0 if it is 0 it will

become 0 that is it the flip flop will

become reset

that is here the output is 1 it will

become 0 it will be resetted it will be

reset

so now same thing will be carried

so till here the same thing will be

carried

so from here

the enable signal is zero so when enable

signal is zero the previous output will

be carried so from here to here the

state of the output is same that is Zero

edition

here it will be zero itself from here to

here so again here we have one so

whenever there is a e n is equal to 1

then only the flip flop is active so

again at this moment so here we can see

that

s is 0 here R is 0 it will follow the

previous state till here the output of

the flip flop is 0 itself

when it reaches here

the r is 1 s is 0 and enable is 1 it

means s is 0 R is 1 means flip flop will

be reset

so already it is in reset

same thing will be continued again till

this point

till this point same thing will be

continued so at this moment

here s is 0 R is 0 again the same thing

will be continued till this point the

same thing will be continued

so at this moment we can see that s is

equal to 1 R is 0 and enable is 1 so

when s is one R is 0 flip flop will set

the flip flop will go high

and it will be high until this point

till this it will be high so here we can

see that after this the enable signal

will become zero when enable will become

0

the flip flop will carry

there is no change no change means flip

flop will carry the same previous output

so it will remains one

here onwards enable is 0 the flip flop

output should be like this so this is

the Q output so the Q Bar output is

always the complement of Q just draw the

complement of this q that is

from here to here it is 0 so here it

will be 1

so from here to here it is 0

from here to this point it is 0 so

complement is 1 so here it will be 1

can draw like this and here onwards it

will be zero

so this is how the flip flop or gated Sr

latch will work now let me derive the

characteristic equation of Sr latch

characteristics equation of Sr latch

so characteristic equation gives the

relation between next state of the flip

flop present state of the Flip Flop and

yes and our inputs

so here we can see that S and R are the

inputs qn is present state of the flip

flop q n plus 1 is next state of the

flip flop characteristic equation gives

the relation between q n plus 1 with q n

s and r so here we'll consider s r and q

n as a input q n plus 1 as a output

so let me consider

this is yes input here we have R and

q n

so we know that this is 0 0 of cell this

is 0 1 1 0 1 1 this is 0 and this is 1.

so this is cell number 0 1 2 3

4 5 and here we have 6 and 7.

so let me ignore the first

these two inputs that is when en is 0

consider only when n is 1 so here we

have

this is 0 1 4 1 the value is one

and for 4 1 0 0 4 4

value is 1 and for cell number five

value is one so for the cell number one

four five the value of the flip flop is

one

let me write

one four five that is one

four five value of the flip flop is one

and four six and seven value is don't

care

for six and seven value is don't care in

all other cells the value is zero

so let me simplify this so here I can do

1 1 x x can be done one square

here this is required the value of this

is so it covers the row one which is

with respect to yes

so here we have one

so this one and this one can together

make a pair

here the value of this is

here R Bar q n that is R Bar q n so

therefore we can write

q n plus 1 is equal to we have S Plus R

Bar q n

R Bar

q n this is the characteristic equation

for Sr latch or Sr

gated Sr latch that is q n plus 1 equal

to S Plus R Bar q n so this is all about

positive level triggered Sr flip flop

flip flop

so in negative level triggered Sr flip

flop the symbol of the SR latch can be

represented as everything is same for

enable here we supposed to put the

circle that Circle indicates

negative H triggered so through Circle

this circle indicates negative is

triggered or enable signal is low so in

that case here the enable signal when

enable signal is one the flip flop is

not active the flip flop will not

respond and the flip flop will be active

only when enable signal is zero so

everything is same only this enable

signal inputs will be zero

so rest s r u n q n plus 1 and state

will be remains same

thank you for watching in my next video

I will discuss about

Edge triggered Sr flip flop you can come

to know the difference between level

triggered and Edge triggered Sr flip

flop thank you for watching