4.5 - Timing Hazards & Glitches

Summary

The video explains timing hazards or glitches in combinational logic circuits, caused by different delay paths through a circuit that result in erroneous behavior before reaching a steady state. Using an example, the speaker demonstrates how varying delays in logic gates can lead to temporary glitches on the output, even when the final result remains correct. The video discusses methods to mitigate glitches, including calculating worst-case delays, balancing path delays, or adding redundant logic. Modern circuits primarily address glitches by evaluating outputs at fixed intervals based on maximum delay calculations.

Takeaways

• 💡 Timing hazards, also known as glitches, occur due to different delay paths in a combinational circuit, causing erroneous outputs before reaching a steady state.
• 📝 In combinational circuits, inputs can change between any arbitrary codes, potentially leading to glitches during the transition from one input to another.
• 🔀 Example: A glitch may occur when transitioning from input code 111 to 110, causing a temporary incorrect output due to varying delay paths.
• ⏳ Gate delays, like the example of 1 nanosecond delay per gate, contribute to the glitch as different paths experience different overall delays.
• 📉 Timing hazards can manifest in three ways: static one glitch (output should remain 1 but momentarily goes to 0), static zero glitch, and dynamic hazards (glitch during a transition).
• 🛠 A common solution to timing hazards is to wait for the maximum delay to allow the output to settle, ensuring accurate output at specific intervals.
• 🔧 Another potential solution is to balance the delay paths by adding buffer circuits, though this approach is challenging due to inherent variations in gate delays.
• 💻 Adding redundant logic that covers interim calculations can also mitigate glitches by holding the output steady while other paths transition.
• ⚙️ Using the complete sum of products, which includes all prime implicants, is a strategy to minimize static timing hazards in combinational circuits.
• ⏱ In modern circuits, the most practical approach to avoid glitches is calculating the worst-case delay and evaluating outputs only at safe intervals.

Q & A

What is a timing hazard in combinational logic?

A timing hazard, also known as a glitch, is an unwanted transition on the output of a digital circuit caused by different delays through various paths, resulting in erroneous behavior before the output reaches a steady state.

How is a minimal sum expression derived from a truth table?

A minimal sum expression is derived by circling groups of 1s in a truth table that can be covered by a single term, excluding the term for the group, and then combining these terms with logical OR operations.

What is an example of a minimal sum expression for a given truth table?

For a truth table with outputs 0 0 0 1 1 0 1 1, a minimal sum expression could be F = B'C + A'BC, where B'C represents the first group of 1s and A'BC represents the second group.

Why might a glitch occur in a digital circuit?

A glitch can occur when different paths through a circuit have varying delays, causing the output to exhibit erroneous behavior before settling at the correct steady-state value.

How does the timing of gate delays contribute to glitches?

Gate delays contribute to glitches because the varying propagation times through different paths in the circuit can cause the output to change temporarily before reaching the correct value.

What is the difference between static and dynamic timing hazards?

Static timing hazards occur when there is an unwanted glitch in an otherwise stable output state (either 0 or 1), while dynamic hazards occur during a transition from one output state to another.

How can timing hazards be mitigated in digital circuit design?

Timing hazards can be mitigated by calculating the worst-case delay and evaluating outputs at intervals that allow for this delay, matching delays through each path, or by using additional logic to cover potential glitches.

Why is it recommended to use a complete sum of products instead of a minimal sum in circuit design?

Using a complete sum of products includes all prime implicants and minimizes the potential for static one or zero timing hazards by ensuring that there is always at least one term that can maintain the correct output during transitions.

What is the role of buffer circuits in mitigating timing hazards?

Buffer circuits can be used to match delays in different paths of a circuit. By introducing additional delay with buffer circuits, the designer can attempt to equalize path delays and reduce the likelihood of glitches.

How do power supply variations affect the timing of digital circuits?

Power supply variations can cause the delay through gates to change, which can lead to unpredictable timing and contribute to the occurrence of timing hazards.