Latches and Flip-Flops 6 - The JK Flip Flop

Summary

The video script delves into the versatility of the JK flip-flop, a fundamental building block in digital electronics used in various applications like shift registers and counters. It contrasts the JK flip-flop with the SR latch, highlighting the JK's ability to avoid unpredictable behavior with invalid input combinations. The script explains the construction of JK latches from both NOR and NAND gates and their transition to flip-flops with the introduction of an enabling input and clock signal. It also demonstrates how the JK flip-flop operates as a toggle device when J and K inputs are combined.

Takeaways

• 🔄 The JK flip-flop is a versatile component used in various applications such as shift registers, ripple counters, event detectors, and frequency dividers.
• 🌐 It is known as the universal programmable flip-flop because it can mimic the behavior of other flip-flop types by manipulating its inputs.
• 🚫 The JK flip-flop overcomes the limitation of the set-reset latch, which can exhibit unpredictable behavior with certain input combinations.
• 🔩 The set-reset latch built from NOR gates has an active-high configuration, while the one built from NAND gates is active-low.
• 🔄 In a set-reset latch, an invalid input combination of both S and R being high can lead to a race condition and unpredictable output states.
• 🔄 The JK latch, a precursor to the JK flip-flop, can be built from both NOR and NAND gates, eliminating the invalid state issue of the set-reset latch.
• 🔄 A JK latch built from NOR gates will oscillate between states when both J and K inputs are high, while a NAND-based JK latch behaves similarly.
• 🔒 Adding an enabling input (E) to the JK latch allows it to respond to J and K inputs only when E is high, effectively gating the latch.
• ⏲️ The JK flip-flop operates on the rising edge of a clock signal, toggling its state when both J and K are high during this transition.
• 📊 A modified truth table can describe the behavior of the JK flip-flop, showing how Q changes on the rising edge of the clock based on J and K inputs.
• 🔄 By connecting J and K together and labeling it as 'T' for toggle, the JK flip-flop can be adapted to create a T flip-flop that toggles state on the rising edge of the clock when T is high.

Q & A

What is a JK flip-flop and why is it considered versatile?

A JK flip-flop is a type of bistable multivibrator that can be used as a shift register, ripple counter, event detector, frequency divider, and more. It is considered versatile because it can be manipulated to behave like other types of flip-flops, overcoming limitations of set-reset latches.

What is the main advantage of a JK flip-flop over a set-reset latch?

The main advantage of a JK flip-flop over a set-reset latch is that it eliminates the issue of unpredictable behavior when both set and reset inputs are high simultaneously, which is an invalid state for a set-reset latch.

How does an SR latch built from NOR gates work?

An SR latch built from NOR gates operates with active high inputs. The output Q is set to 1 when a high pulse is applied at S, and reset to 0 when a high pulse is applied at R. The latch holds the last value when both inputs are low.

What is the problem with an SR latch when both S and R inputs are high?

When both S and R inputs of an SR latch are high, it creates an invalid state where the latch is told to store both 1 and 0 at the same time. This results in Q and not Q both becoming 0, leading to unpredictable behavior.

How does an SR latch built from NAND gates differ from one built from NOR gates?

An SR latch built from NAND gates is active low, meaning S and R should be kept high and a low pulse at either S or R will set or reset the latch, respectively. It avoids the same invalid state issue as the NOR-based latch when both inputs are high.

What is a JK latch and how does it differ from a JK flip-flop?

A JK latch is a modified version of an SR latch with added AND gates at the inputs, labeled J and K for set and reset. It differs from a JK flip-flop in that it does not have a clock signal and can oscillate between states when both J and K are high.

How does a JK flip-flop solve the invalid inputs problem of an SR latch?

A JK flip-flop solves the invalid inputs problem by using AND gates at the inputs, which ensures that when both J and K are high, the flip-flop toggles between states rather than resulting in an invalid state.

What is the purpose of the enabling input 'E' in a gated JK latch?

The enabling input 'E' in a gated JK latch is used to control when the latch responds to the J and K inputs. The latch only updates its state when 'E' is high and the clock signal is on the rising edge.

How can a JK flip-flop be adapted to create a toggle flip-flop?

A JK flip-flop can be adapted to create a toggle flip-flop by connecting J and K together to form a single toggle input. This results in the flip-flop changing state only when the toggle input is high during the rising edge of the clock signal.

What is the significance of the rising edge detector in a JK flip-flop?

The rising edge detector in a JK flip-flop ensures that the flip-flop only reacts to the inputs during the rising edge of the clock pulse. This prevents the flip-flop from oscillating uncontrollably when J and K are both high.

How is the toggling behavior of a JK flip-flop described in its truth table?

The toggling behavior of a JK flip-flop is described in its modified truth table, where a rising edge of the clock pulse causes the output Q to change to its opposite state when both J and K are high, while leaving Q unchanged otherwise.

Outlines

00:00

🔄 Understanding the JK Flip-Flop and Its Versatility

The JK flip-flop is a highly versatile component in digital electronics, serving various functions such as shift registers, ripple counters, event detectors, and frequency dividers. It is known as the universal programmable flip-flop due to its ability to mimic other flip-flop types through input manipulation. Unlike the set-reset latch, which can exhibit unpredictable behavior with certain input combinations, the JK flip-flop overcomes this limitation. The script explains the set-reset latch's operation and its issues with invalid input combinations, which can lead to a race condition and unpredictable output states. The JK flip-flop is then introduced as a solution to these problems, highlighting its similarity to the set-reset latch but with improved input handling.

05:01

🛠 Building and Operating the JK Latch

This section delves into the construction of a JK latch, starting with an active-high SR latch made from NOR gates, and then adding AND gates to create the JK functionality. The JK latch demonstrates the fundamental characteristic of the JK flip-flop: the ability to set and reset the output and to toggle between states when both inputs are high. The script also covers building a JK latch from an active-low SR latch using NAND gates, which results in a functionally identical device to the NOR-based version. The importance of eliminating the invalid state where both Q and not Q could be high simultaneously is emphasized, showcasing the reliability and functionality of the JK latch in various configurations.

10:04

🕒 Clock Signal Integration in the JK Flip-Flop

The integration of a clock signal is crucial for transforming a JK latch into a JK flip-flop. The script uses a timing diagram to illustrate the flip-flop's behavior under different input conditions and clock signals. It explains how the flip-flop only reacts to inputs during the rising edge of the clock pulse, effectively toggling the output Q between states. A modified truth table is introduced to describe this toggling behavior, emphasizing that the JK flip-flop will only change state when both J and K inputs are high during a rising clock edge. The script concludes by showing how the JK flip-flop can be adapted to create a toggle flip-flop, where J and K are connected to form a single toggle input.

Keywords

💡Flip-flop

A flip-flop is a type of circuit in digital electronics that has two stable states and can be used to store binary data. In the video, flip-flops are central to the discussion, with the JK flip-flop being highlighted as a versatile component used in various digital systems like shift registers and counters.

💡JK Flip-flop

The JK flip-flop is a specific type of flip-flop that can be programmed to act as other types of flip-flops. It is called 'universal' because it can be configured to function as a set-reset, toggle, or clocked flip-flop. The video explains how the JK flip-flop overcomes the limitations of the set-reset latch.

💡Shift Registers

Shift registers are a sequence of flip-flops that store and shift data one bit at a time. They are used for serial-to-parallel or parallel-to-serial data conversion. The script mentions that the JK flip-flop is used in shift registers, emphasizing its versatility.

💡Ripple Counters

A ripple counter is a type of binary counter where each flip-flop's output depends on the output of the previous flip-flop. The video script mentions ripple counters as one of the applications of the JK flip-flop.

💡Event Detectors

Event detectors are circuits that can identify and respond to specific events or conditions. In the context of the video, the JK flip-flop can be used to create an event detector due to its ability to change state based on input conditions.

💡Frequency Divider

A frequency divider is a circuit that divides the input frequency by a certain factor. The JK flip-flop, with its toggling ability, can be used to create a frequency divider, as mentioned in the video script.

💡Set-Reset Latch

A set-reset latch is a type of memory element with two inputs: set and reset. The video script explains the limitations of this latch, particularly the issue of unpredictable behavior when both inputs are high simultaneously.

💡Propagation Delays

Propagation delays refer to the time it takes for a signal to pass through a logic gate or a circuit. The video script mentions that the speed of oscillation in a JK flip-flop depends on the propagation delays within the logic gates.

💡Oscillator

An oscillator is a circuit that produces an output signal at a specific frequency. The video script describes how a JK latch can be used to create an oscillator due to its ability to switch states when both inputs are high.

💡Rising Edge Detector

A rising edge detector is a circuit that triggers an output when it detects a transition from low to high in the input signal. The video script explains how to modify a JK flip-flop to respond only to the rising edge of the clock signal, which is essential for its operation as a flip-flop.

💡Truth Table

A truth table is a mathematical table used in logic to show all possible values of inputs and their corresponding outputs for a particular function. The video script uses a modified truth table to describe the behavior of the JK flip-flop under different input conditions.

💡Toggle Flip-flop

A toggle flip-flop is a type of flip-flop that changes its output state each time it receives a clock pulse. The video script describes how the JK flip-flop can be adapted to function as a toggle flip-flop by connecting the J and K inputs together.

Highlights

The JK flip-flop is a versatile device used in various applications such as shift registers, counters, and frequency dividers.

It is known as the universal programmable flip-flop due to its ability to mimic other types of flip-flops by manipulating inputs.

The JK flip-flop overcomes the limitation of unpredictable behavior with invalid input combinations, unlike the set-reset latch.

An SR latch built from NOR gates is susceptible to invalid states when both set and reset inputs are high.

The output of an SR latch can become unpredictable in a race condition when both inputs return to zero simultaneously.

An SR latch built from NAND gates also faces issues with invalid input combinations, leading to unstable outputs.

The JK latch, a precursor to the JK flip-flop, eliminates the invalid state issue by introducing new inputs J and K.

A pulse at K in a JK latch will reset the latch, similar to the reset function in an SR latch.

When both J and K inputs are high, the JK latch oscillates, which is a key feature for its operation as a flip-flop.

The JK flip-flop can be built from both NOR and NAND gate-based SR latches, with functionally identical results.

Adding an enabling input to a JK latch, similar to an SR latch, controls its response to J and K inputs.

A clock signal at the enabling input turns a gated JK latch into a functional JK flip-flop.

The JK flip-flop's behavior can be visualized through a timing diagram, showing how it responds to clock signals and input changes.

The JK flip-flop only reacts to inputs on the rising edge of the clock pulse, preventing uncontrollable oscillation.

A modified truth table for the JK flip-flop illustrates its toggle effect and input conditions for state changes.

The JK flip-flop can be adapted to create a T flip-flop, which toggles state only when the input is high at the rising edge of the clock.

Transcripts

when it comes to flip-flops the JK flip

flop is one of the most versatile

it's widely used in shift registers

Ripple counters event detectors

frequency dividers and more

the JK flip-flop is often referred to as

the universal programmable flip-flop

because by simply manipulating its

inputs it can be made to behave like

other types of flip-flop

in essence the JK flip-flop is very

similar in operation to the set reset

latch but it overcomes a serious

limitation of the set reset latch namely

that an invalid combination of inputs

can result in unpredictable Behavior

let's remind ourselves of this

limitation here's an Sr latch built from

nor Gates

the inputs S and R are normally kept low

and a high pulse is applied at one or

the other in order to set or reset it

the latch is said to be active High

in this case the value of the output Q

is 1 so the latch is currently storing a

one

the value of not Q should always be the

opposite of Q not Q is currently zero

a short pulse is applied at R to reset

the latch s is still zero

trace the highs and lows through the

cross-connected nor Gates and you'll see

that the output at Q changes to zero

when the reset pulse is removed R

becomes zero again but the outputted Q

is still zero the latch is now holding

on to the zero

when a set pulse is applied at s the

output at Q changes to 1. the latch is

now storing a one

however we have a problem when both S

and R are made one at the same time with

this combination of inputs we're

effectively telling the latch that we

want to store one and zero

simultaneously which of course is

nonsense the output at Q can only have

one value

in reality the outputted Q will become

zero but not Q will also become zero

eventually when both inputs fall back to

zero the resting state of the latch will

depend on which input Falls to zero

first if R Falls to zero first Q will

become one if s Falls to zero first Q

will become zero

but if both inputs fall to zero at

exactly the same time then we'll have a

race condition the nor Gates will be

racing to feed each other their new

output

one of them will eventually win because

of imperfections in the circuitry or

external factors like temperature but

it's impossible to know which one if

both inputs become High Then Fall to

zero at the same time the next state of

the latch is impossible to predict

this is a state that the latch should

never be in it's invalid

most of the time inputs S and R should

be both resting at zero and only

momentarily should one or the other

become one

at any point in time the output at Q

should be one or zero and not Q should

always be the opposite of Q

here's an Sr latch built from nand Gates

this version of an Sr latch is active

low S and R should be kept High most of

the time and the drop in voltage at s

that is a low pulse at s will set it a

low pulse at R will reset it

at the moment the outputted Q of this

latch is zero so the latch is currently

storing a zero

when s becomes zero momentarily the

output at Q becomes one when s returns

to its normal high state q is still one

the latch is now storing a one

when R is made low for a moment then the

output at Q is changed to zero

R can then return to its normal high

value and the latch is now storing a

zero

if both S and R become zero at the same

time we have a similar problem to the

one that we saw with an Sr latch built

from nor Gates both q and not Q become

one

if S and R return to their normal high

State at the same time it's impossible

to predict the final value of Q with a

nand-based Sr latch the input

combination s equals zero and R equals

zero is invalid

here are the two methods of building an

Sr latch side by side

so how does a JK flip-flop solve the

invalid inputs problem

well before we think about this let's

take a look at something that we will

call for want of a better name a JK

latch

here's our simple active High Sr latch

based on nor Gates

we'll add a pair of and Gates

immediately after the inputs

then we'll feed the value of output Q

into the top and gate and the value of

not Q into the bottom and gate

finally we'll re-label the inputs J and

K J to set K to reset

this is a JK latch it's not a flip-flop

yet but it does illustrate a fundamental

characteristic of the JK flip-flop

a pulse at K will reset the latch

and the output at Q will become zero

just like an Sr latch

a pulse at J will set the latch

making the outputted Q equal to 1.

if the latch is already storing a one

and another set pulse is applied J

it will have no effect whatsoever

but if both inputs are made high at the

same time

the value of Q will become zero and if

both inputs remain high the latch will

switch back to the opposite State the

outputted Q is 1 again

keeping both inputs high will cause the

latch to switch repeatedly from one

state to the other the output of the

latch is now oscillating between 1 and

0.

the speed of oscillation depends on

propagation delays within the logic

gates and the connecting circuitry but

it is of course very quick

this so-called JK latch is not

particularly useful unless you wanted to

build an oscillator like this and to be

honest there are more efficient ways to

build an oscillator

nevertheless we've eliminated the

possibility of Q and not Q having the

same value at the same time

and we're a step closer to the JK

flip-flop

before we do see how to create something

very useful let's try to build a JK

latch from an active low Sr latch

consisting of nand gates it will help us

to understand the possibilities

we'll add a pair of nand gates

immediately after the inputs

then we'll feed the value of output Q

into the bottom nand gate and the value

of not Q into the top nand gate

as before we'll re-label set and reset

as J and K

and again we have a JK latch but this

time we've changed the way the

nand-based SR latch works it's now

active High instead of active low

this JK latch is now functionally

identical to the JK latch that we built

from nor Gates

there's a zero at output Q so the latch

is currently storing zero

to set the latch we apply a high pulse

to J

now there's a one at Q

to reset the latch we apply a high pulse

to K and when K falls back to zero Q is

zero again

when both inputs are high then just like

the nor based JK latch the nand-based

latch oscillates between the two states

again we've built an oscillator

but more importantly we've eliminated

the possibility of Q and not Q having

the same value at the same time

here are our two JK latches side by side

remember they are functionally identical

they do the same thing

in the second video of this series we

saw how it was possible to add an

enabling input to a simple Sr latch this

involved a pair of steering Gates

we can do something similar here

the and Gates of the nor based latch on

the left now have three inputs each

all of the inputs of a three input and

gate must be one in order to get a one

out so the new input e must be high in

order for the latch to respond to

anything from j or k

the nand gates of the nand-based latch

on the right also have three inputs each

in order for the output of a three input

nand gate to drop to zero all of the

inputs must be one

so again e must be high in order for the

nand-based latch to respond to any

changes in j or k

the switching behavior of these latches

hasn't changed at all they simply have

to be enabled before they'll do anything

to turn a gated JK latch into a JK

flip-flop all we need to do is supply an

appropriate clock signal at the enabling

input

let's take a closer look at how this

works we can focus on either one of

these designs now they do the same thing

a timing diagram is a convenient way to

examine the behavior of a JK flip-flop

the top chart colored green represents

the clock signal the bottom red chart is

the value of output Q which you can see

starts off high

the values of inputs J and K are the

purple charts in between

in this scenario when input K goes High

there's no change at Q because the clock

is low

the flip-flop is momentarily disabled

but when the clock does go high the

reset signal gets through the and gate

and Q Falls to zero

Q then remains low regardless of what

the clock is doing and what's going on

at input K as long as J stays low but

when J is high K is low and the clock is

high the value of Q becomes 1 again

when inputs J and K and the clock are

all high at the same time the value of Q

begins to oscillate rather

uncontrollably

to take advantage of this oscillation we

need a flip-flop that will only react to

the inputs while the clock signal is

changing from low to high in other words

on the rising edge of each pulse

in the fourth video of this series I

showed you how to build a rising Edge

detector using an and gate and a not

gate this relies on the fact that a not

gate doesn't invert its input

immediately for a very brief period a

matter of nanoseconds the output of the

not gate is the same as its input so for

only a very brief period is the output

of the and Gate High we've effectively

shortened each clock pulse to just a few

nanoseconds

here's a new timing diagram only the

rising edge of each clock pulse has any

effect so that's all you can see on the

top chart

notice that when J and K are both High a

clock pulse will cause the flip-flop to

toggle from one state to another

way to describe this behavior is with a

modified truth table there's a column

for the rising edge of each clock pulse

the column labeled Q next indicates what

Q will become depending on the inputs

if both J and K are 0 Q remains

unchanged

across in the clock column means

anything other than the rising Edge and

crosses in columns J and K mean whatever

the values they'll have no effect Q

won't change

if however J and K are both one a rising

Edge will cause Q to change to its

opposite state

this is the definitive toggle effect of

the JK flip-flop

finally I want to quickly mention how

the JK flip flop can be easily adapted

to create a new device

by simply connecting together J and K to

make one input we now have a device that

will only toggle from one state to the

other when the input is high at the

rising edge of the clock

we can re-label the input t for toggle

we now have a type flip flop