Logic implementation using Programmable Logic Array (PLA)

Summary

In this HDL digital circuit design course, Professor Shilpakar Rudar from MIT Academy of Engineering, Pune, introduces Programmable Logic Array (PLA), a versatile IC that allows users to configure logic gates and flip-flops for various functions. The lecture covers PLA's structure, types, and programming process, including using Boolean functions and K-maps for optimization. It also discusses PLA's limitations, such as complexity, speed, power consumption, and scalability, alongside its advantages like flexibility, customization, compact design, high integration, and a simplified design process, providing a comprehensive understanding of PLA's role in digital logic implementation.

Takeaways

• 📘 The course is about HDL digital circuit design, specifically focusing on Programmable Logic Array (PLA).
• 🔍 PLAs are ICs that contain a large number of gates and flip-flops configurable by the user to perform various functions.
• 💡 The lecture explains the concept of programmable logic devices (PLDs), which include PLAs and other types like PALs and PLOs.
• 🌐 The programmability of PLAs involves both AND and OR arrays, which can be either fixed or programmable, defining different types of PLDs.
• 🔑 The process of programming a PLA involves using programming software or a programming process to configure the logic gates and switches.
• 🛠️ The script provides an example of implementing a Boolean function using PLA, detailing the process of generating product terms and connecting them to OR gates.
• 🔄 The use of XOR gates in PLAs is explained for inverting logic at the output side without the need for additional NOT gates.
• 📊 The script includes a step-by-step guide on using a truth table and Karnaugh Maps (K-maps) to derive Boolean equations for PLA implementation.
• 🚧 The limitations of PLAs are discussed, including complexity and cost, speed limitations due to logic delays, higher power consumption, and scalability issues.
• 🛑 Advantages of PLAs highlighted include flexibility in logic implementation, customization to meet specific requirements, compact and high integration design, and a simplified design process.
• 👨‍🏫 The lecture is delivered by Professor Shilpakar Rudar from the School of ENTC Engineering at MIT Academy of Engineering in Alandi, Pune.

Q & A

What is the main topic of the course presented in the script?

The main topic of the course is Programmable Logic Array (PLA) and how to program combination logic within it, including its limitations and advantages.

What does the acronym 'PLD' stand for in the context of the script?

PLD stands for Programmable Logic Device, which is an IC containing a large number of gates and flip-flops that can be configured by the user to perform different functions.

What are the different types of programmable logic devices mentioned in the script?

The different types of programmable logic devices mentioned are Programmable Array Logic (PAL), Programmable Logic Array (PLA), and Programmable Read-Only Memory (PROM).

What is the role of the AND and OR arrays in a PLA?

In a PLA, both the AND and OR arrays are programmable. The AND array generates product terms based on the inputs, which are then fed into the OR array to produce the required logic functions.

How can the script's explanation of Boolean functions be utilized in circuit design?

The explanation of Boolean functions in the script can be used to implement specific logic functions using a PLA by determining the required product terms and connecting the AND and OR gates accordingly.

What is the purpose of the XOR gate mentioned in the script?

The XOR gate is used to provide the option to invert the output logic if required, without needing an additional NOT gate, by connecting one of its terminals to logic one or zero.

How does the script describe the process of implementing digital logic using a PLA?

The script describes the process by starting with a truth table, using a Karnaugh map (K-map) to simplify the Boolean equations, and then programming the AND and OR arrays in the PLA according to these equations.

What are some limitations of using a PLA as mentioned in the script?

Limitations include complexity and cost due to a large number of programmable links, speed limitations due to multiple levels of logic, higher power consumption, and difficulty in scaling for very large designs compared to devices like FPGAs.

What advantages does the script highlight for using a PLA?

Advantages highlighted include flexibility in logic implementation, customization to meet specific requirements, compact design, high integration enabling complex digital systems on a single chip, and a simplified design process due to programmability of the AND and OR arrays.

How does the script explain the optimization of logic functions in a PLA?

The script explains optimization by showing how common product terms in Boolean equations can be shared, reducing the number of AND gates needed, thus simplifying the circuit.

What is the significance of the script's mention of the programmability of both AND and OR arrays in a PLA?

The programmability of both AND and OR arrays in a PLA allows for high flexibility and customization in logic design, making it suitable for a wide range of applications and enabling the implementation of complex digital systems.

Outlines

00:00

📚 Introduction to Programmable Logic Array (PLA)

The first paragraph introduces the topic of the video script, focusing on the concept of Programmable Logic Array (PLA) within HDL digital circuit design. Shilpakar Rudar, the assistant professor at MIT Academy of Engineering, explains the basics of PLA, which is a type of programmable logic device (PLD) containing a large number of gates and flip-flops that can be configured by users. The explanation includes the programmability of both AND and OR arrays, the use of programmable switches to implement logic functions, and the types of PLAs including AND-OR-INVERT (AOI) and other variations. The paragraph sets the stage for a deeper dive into PLA programming and its applications.

05:01

🔍 Exploring PLA Configuration and XOR Gate Function

This paragraph delves into the configuration of PLA, discussing the programmable AND and OR arrays and their roles in creating combination logic. It explains how inputs are provided to the AND array, which can be complemented using inverters, to generate product terms. These terms are then fed into the OR array to produce the desired output functions. The paragraph also introduces the use of an XOR gate for inverting logic outputs when necessary, providing a truth table for the XOR gate and explaining how its inputs can be manipulated to achieve the desired output inversion. This section clarifies the technical aspects of PLA configuration and the flexibility offered by the inclusion of an XOR gate for output modification.

10:02

🛠️ Implementing Digital Logic with PLA using K-Maps

The third paragraph presents a step-by-step guide on how to implement digital logic using a PLA, with a practical example involving a truth table for two functions based on three inputs. The explanation covers the use of K-maps (Karnaugh maps) for simplifying Boolean equations derived from the truth table. It details the process of filling out the K-map, applying grouping rules to minimize the logic expression, and optimizing the circuit by reducing the number of product terms. The summary also touches on the use of complements to further simplify the logic design, leading to a more efficient implementation within the PLA.

15:04

🚀 Advantages and Limitations of PLA in Digital Circuit Design

The final paragraph summarizes the advantages and limitations of using PLA in digital circuit design. It acknowledges the flexibility and customization capabilities of PLA due to its programmable AND and OR arrays, making it suitable for a wide range of applications. The paragraph also highlights the compact and high integration design of PLA, which allows for complex digital systems to be implemented on a single chip. However, it also discusses the limitations, including complexity and cost due to the large number of programmable links, potential speed issues due to multiple logic levels, higher power consumption, and scalability challenges compared to more advanced devices like FPGAs. The summary concludes by emphasizing the simplified design process facilitated by PLA's programmability.

Keywords

💡HDL digital circuit design

HDL, which stands for Hardware Description Language, is a specialized language used to describe the structure and behavior of electronic systems such as digital circuits. In the context of the video, HDL digital circuit design refers to the process of creating digital circuits using a hardware description language. The video's theme revolves around the design and programming of digital circuits, specifically using Programmable Logic Array (PLA), which is a type of digital logic that can be programmed to perform various functions.

💡Programmable Logic Array (PLA)

A Programmable Logic Array (PLA) is an integrated circuit that contains a grid of logic gates, both AND and OR gates, which can be programmed to perform a variety of logical functions. The video explains how to program PLAs to implement specific combinational logic. PLAs are significant in the video as they are the main topic and the focus of the course content.

💡Combinational logic

Combinational logic refers to a type of digital logic circuit where the output is determined by the current input values only, without any memory of past inputs. The video discusses programming PLAs to implement combinational logic, which is a fundamental concept in digital circuit design.

💡AND array

An AND array is a set of AND gates arranged in a matrix form within a PLA. It is responsible for generating product terms based on the inputs provided. In the video, the AND array is described as being programmable, allowing for the creation of various product terms that are essential for implementing the desired logic functions.

💡OR array

An OR array is a collection of OR gates that combine the output of the AND array to produce the final output of the PLA. The video explains that in a PLA, the OR array is also programmable, which means that it can be configured to combine the product terms from the AND array in various ways to achieve the required logic functions.

💡Boolean function

A Boolean function is a mathematical function that takes Boolean values (true or false, often represented as 1 or 0) as inputs and produces a Boolean value as output. The video uses Boolean functions as examples to illustrate how to program PLAs to achieve specific logical operations.

💡Karnaugh map (K-map)

A Karnaugh map is a graphical method used to simplify Boolean algebra expressions. The video mentions using K-maps to solve for the equations needed to program the PLA based on a given truth table. K-maps are essential in minimizing the complexity of the logic and reducing the number of gates required.

💡Product term

A product term in Boolean algebra is a conjunction (AND operation) of literals or variables. In the context of the video, product terms are generated by the AND array and are used as inputs to the OR array to produce the final output of the PLA.

💡Inverter

An inverter is a digital logic gate that performs the NOT operation, inverting the input signal to produce the opposite output. The video explains that inverters are used within the PLA to generate complements of inputs, which are necessary for creating the required product terms.

💡XOR gate

An XOR gate is a logic gate that outputs true or 1 only when the number of true inputs is odd. In the video, an XOR gate is used to invert the output of the OR array if needed, providing flexibility in the design to achieve the desired logic function.

💡Optimization

Optimization in digital circuit design refers to the process of simplifying and improving the circuit to reduce the number of components, cost, and power consumption, while maintaining the required functionality. The video discusses optimizing the PLA by reducing the number of product terms and gates, which is an important aspect of efficient circuit design.

💡Limitations

The video outlines several limitations of using PLAs, such as complexity and cost due to the large number of programmable links, speed limitations due to multiple levels of logic, higher power consumption due to dense interconnections, and scalability issues when compared to more advanced programmable devices like FPGAs.

💡Advantages

Despite the limitations, the video also highlights the advantages of PLAs, including flexibility in logic implementation, customization to meet specific requirements, compact design, high integration enabling complex systems on a single chip, and a simplified design process due to the programmability of both AND and OR arrays.

Highlights

Introduction to Programmable Logic Array (PLA) and its role in HDL digital circuit design.

Explanation of programmable logic devices (PLDs) as ICs containing configurable gates and flip-flops.

Description of how PLDs can be programmed using software or a programming process.

Differentiation between types of PLDs: PAL, PLA, and PLO based on the programmability of AND and OR arrays.

Visual representation of fixed and programmable logic arrays in diagrams.

The process of programming AND and OR arrays in a PLA to implement specific logic functions.

Use of Boolean functions to demonstrate the implementation of logic in PLA.

Role of XOR gates in inverting logic outputs when required.

Explanation of how to implement digital logic using PLA with an example truth table.

Utilization of Karnaugh Maps (K-maps) for simplifying Boolean equations from a truth table.

Optimization of circuit design by reducing the number of product terms using complements.

Cross-connections in programmable AND and OR arrays to implement the logic equations.

Limitations of PLA including complexity, cost, speed, power consumption, and scalability.

Advantages of PLA such as flexibility, customization, compact design, high integration, and simplified design process.

Practical example of implementing combination logic using PLA and optimizing the circuit.

Conclusion summarizing the key points of PLA's functionality, limitations, and advantages.

Invitation to the next session and encouragement for continued learning in digital circuit design.

Transcripts

welcome to the course of HDL digital

circuit design today's topic is

programmable logic array I'll be

explaining how to program particular

combination logic in pla and its

limitation and advantages myself

shilpakar rudar assistant Pro Professor

School of entc Engineering MIT Academy

of engineering alandi Pune so moving

ahead with the topic programmable logic

uh array so in the previous section we

have seen what is mean by plld

programmable uh logic devices uh which

is an IC containing large number of

gates flip flops which can be configured

by the user to perform different

functions and it is a single IC on which

you are implementing digital logic and

uh here uh there are programmable

devices which can be programmed using

programming software or programming

process so here you are able to see on

the left hand side this diagram indicat

GES that plld is there in which you are

having logic gates and programmable

switches inputs will be given to the

input side and depending upon logic you

are implementing uh that will be

programmed by making switches on and off

and that way you'll be getting your

output that is the function over here at

the output side now there are different

types of PD as we have seen in the

previous section previous lecture that

is programmable array logic programmable

logic array and pron

basic logic uh device over here is the

and array and or array depending upon

which is programmable and which is fixed

or both are programmable depending upon

that we are defining which type of uh

PLS are that so uh over here you are

able to see that is yellow indicates fix

uh array logic and blue color indicates

the programmable one so when and array

is fixed and or array is programmable

then it is a programmable readon memory

that is one type of plld second you are

able to see that and array is

programmable and or array is fixed at

that time that particular plld is

programmable array logic and when both

are programmable as you are able to see

green color or blue color whatever you

are able to see so that is both are

programmable that you are able to

program and array as well as our array

then it is called as a pla now we are

starting with the pla programmable array

uh programmable logic array here you are

able to see this is and array and this

is or array in pla both are programmable

and that's why it is shown by this color

here input to the and array are shown by

the N inputs so here there might be

multiple input present each uh input can

be inverted so if I'm giving input a b

and c so I am able to generate a bar B

Bar C bar also because of inverter

present so these are what are the number

of inputs to the and gate now it will be

generating K product terms over here and

that output will be given to the orgate

so number of orgate will depend upon

number of functions you require so here

I will be explaining this things uh

using this Boolean function suppose you

need to implement this Boolean function

means I am having function w X and Y so

there are three functions that is three

output I require that's why I require

three orgate over here so array of

orgate will will be having three input

over there for the r next over here um

we are having how many product terms so

1 2 3 4 5 6 7 that way I'll be requiring

seven and Gates over here because I

require seven product terms now when I

am giving a b c d over here because a b

c and d these are the inputs available

uh because of this inverter it will be

generating a bar B Bar C Bar D Bar also

so whenever in the product terms I

require complement uh of C complement of

D that is inverted uh D so it will be

possible using this inverter once that

product terms are getting generated that

will be given to the r input over here

so for generating W function over here I

require to apply this product term coms

over here so product term generated from

this particular and gate will be given

to this and one input of orgate and

second uh productor will be given to the

second input of orgid and that way this

will be the function W in the same way

I'll be generating X and Y so I require

total three or gate at the output side

or in our array so hope the things are

clear now one question is over here that

why this exor gate is shown because this

is the orgate and this I told you that

depending upon function you'll be having

that many or Gates over there but here

you are able to see the xor git now what

is the role of this xor gate now as this

is the plld D which is over here it's a

pla sometimes you require the inverted

logic at the output side there should

not be any requirement of not get I for

inverting that logic and that's why this

inversion is provided using this xor

gate now here for your reference I have

shown uh truth table of xor gate where 0

0 gives the output 0 0 1 gives the

output 1 1 Z gives the output one and 1

one is uh uh for one one output is one

uh sorry 0 so 0 1 1 0 you are able to

see it or not I'm not that way sure so

over here so you're able to see 1 one

output is zero so now just check if my

output is over over here and I want that

to be inverted so I need to connect one

terminal of this xor gate to the logic

one so that whatever data I am getting

over here will get inverted now how that

is possible so over here you are able to

see when one of the input of your XR

gate is zero connected fixed to the zero

output you'll be getting depending upon

whatever present on the second terminal

that is if zero is present you'll be

getting zero and one is uh given then

you'll be getting one so consider the

same logic over here if I have connected

one input of xor gate to the zero that

is over here suppose this is zero and

this link is closed so I have connected

it to the zero meaning of that whatever

coming on the second terminal that here

it is mentioned by B so same output

you'll be getting over here so if I'm

having one over here I'll be getting one

so there will not be inverted output but

if I want my logic to be inverted that

is my requirement and don't want to use

uh extra not gate over there so that

will be done through this xor gate now

suppose I'm connecting one of the

terminal to logic one one of the

terminal of this X or get to logic one

so see over here you are having one

connected to one of the terminal so

whatever present on the second input

will get inverted uh at the output so if

zero is given one you'll be getting when

one is given zero you'll be getting so

here you are able to see same thing if

one is connected to the the one terminal

of XR G then whatever data you are

getting over here that is getting

inverted at this particular time um

output so that there is no need of extra

not gate connection hope the things are

clear to

you moving ahead with the next slide now

if you want to implement any logic

digital logic using pla so how to

implement it so for that I have taken

one example here you are able to see

that one truth table has been given

inputs are a b c and two functions are

there fub1 and FS2 now as there are

three inputs there are total eight

possibilities that is 0 0 0 to 111 and

depending upon that you are able to see

this outputs are present now whenever

truth table is given and whenever you

need to have a equation out of that you

need to solve it using uh kmap and hope

the Kap concept is uh already uh you

know in the first year itself but just

for your understanding I'll be briefing

in uh short so here as there are eight

options available so you need to have a

block of 8 over here 2 by 4 over here so

whatever is the MSB you need to write it

over here 0 one and whatever is the LSB

bits are there b c you need to write

here as there is only one variable

options are zero and one as there are

two variables options are 0 0 0 1 1 0

and 1 1 here you you using gray

coding that is after 01 I'm not writing

1 Z I'm writing 1 one because if I'm

writing it near to this 0 1 and 1 Z both

will get cancell and that's why your

equation will not be proper and that's

why you need to use binary uh coding

over here uh gray code over here now how

to solve it as you know that a is the uh

MSB and B and C are the least

significant bits over there so 0 0 0 for

how many functions you are having that

many kmaps you need to draw so there are

two functions F1 and F2 that's why there

are two kmaps has been drawn so here 0 0

0 indicates this z b is also Z and C is

also Z means this particular block will

be 0o again 0 0 1 then this is 1 0 1 1

this is three 0 1 0 that is in binary 0

1 0 in decimal it is two like ways you

need to right at the corner the number

of that block so that it will be easy

for you to um put that outputs over

there so this is 0 1 2 3 4 5 6 and 7

just do it by your own and just uh uh

see whether it is coming same or not so

according to this I'll be writing F1 uh

output over here so 0 0 0 output is one

that's why in this box it is written one

because this is this is the zero block

first block you are having one again it

has been it has been written like that

for two it is one and this is three

because of gray code and this is two

that's why it is one that way you need

to fill up this particular blocks over

there and then you need to apply uh the

grouping uh rules over there so you can

make this as a one group you can make

this as a one group and you can make

this and this as a one

group whenever you are solving you need

to solve in this way I'll be explaining

this particular part over here what is

the uh equation for this that is one one

if I'm grouping this 1 one so 0o and one

that is a is z a is one so that is

getting cancelled and you are having Z 0

that is B bar and C bar so that's why

this particular equation uh in which you

are getting B bar and C bar plus because

this equation has been solved this

grouping has been solved then solve this

grouping now here a is what zero 0 means

a bar and here 0 0 and 0 1 where 0 0 is

constant but this Z is changing with one

and that's why C is changing from 0 to

one so whatever is changing just uh

remove that and whatever is the constant

you need to take it that is B bar so a

bar and B bar this is what is your this

answer of this particular group then

solve this this and this in same way

you'll be getting a bar c bar now if you

want to complement you can complement if

you want to leave it like that just

leave it so I'll be telling you why they

have taken like this uh over there now

same way you need to solve F2 and after

solving you are getting F2 as a A+ a C+

a bar B Bar C bar why you are getting a

bar B Bar C bar because there is no

group form for this this is the single

um digit you are having there is no

grouping possible and that's why this is

a bar B Bar C bar because 0 0 0 and

that's why it is coming in three um bits

over there now uh you need to try to

reduce the implementation as far as

possible so over here if I'm taking this

equation and this equation so number of

product terms are 1 2 3 4 5 6 but if I'm

taking complement of this which is over

here F1 bar is find uh written so a bar

B bar is written as a Ab a bar c bar is

written as a AC B Bar C bar is written

as a BC so in this equ equation and in

this equation you are able to see ab and

AC are common and that way you are

reducing two and Gates over there and

that is uh very much required to

optimize the uh circuit so here final

output you are able to see AB plus AC

plus uh BC and this is the second one

now moving ahead with this thing now as

you have got this particular thing out

of which two are common and that's why

it is taken once and that's why total

product terms requir are 1 2 3 and and

four over here you are able to see and

array and this or array both are

programmable and that's why we are

making the cross connections over here

uh by this way so both are programmable

if that is dot it is fixed now as I told

you at the input side you are giving a

as well as its complement so this is

shown by this particular um figure or

symbol and depending upon your product a

b so I'll be taking this a and this B

over here and I'll be shorting this a

short this B short means this is my ab

so it is written over here same way AC

same way BC and same way a bar B Bar C

and that way over here for fub1 I

required AB AC and a bar B Bar C so it

is given to the one orgate and second it

has been given to the second orgate

now so whatever function you want to

complement that way you need to program

this xor gate so if you want Inver then

connect one of the terminal of X orgate

with one and if you want to give as it

is then connect it with the zero and

rest of the input you need to connect

the output of this orgate so that way

complement function is possible over

here now we have seen how to implement

uh combination logic using pla so what

are the limitations of this particular

pla so you are able to see the first

limitation is complexity and cost that

is pla can be complex and costly to

manufacture due to large number of

programmable links because you need to

program all and array links and all or

array that's why it is uh somewhat uh

large number of links uh you need to

program so it is somewhat complex and

costly second point that is the speed

the multiple level of logic within the

pla can introduce delays making them

slower compared to the some of the types

some of these uh plds that is fpga p

over there so as you are uh programming

all and array and all or array so

somewhat speed limitation will be there

it will not be that way faster but it

will be making it somewhat slower third

point that is the power consumption the

dense interconnection of logic gates can

result in higher power consumption which

might not be suitable for low power

application so because of density over

here the power consumption will be more

next is scalability pla may not be

easily scaled for very large designs

especially when compared to more

advanced programmable devices like fpga

so you are not able to scale it as uh

far as the fpga which is used for

implementing complex logic so that is

the next limitation now what are the

advantages first advantages you are able

to see that is flexibility in logic

implementation as both the arrays and

and or are programming able so

flexibility is very high over there so

you are able to program both the arrays

then customization over here that is

second Point user can customize the

logic design to meet specific

requirements making pla suitable for a

wide range of application so over here

customization is possible because you

are able to program both the arrays

compact design pla allows for the

implementation of multiple logic

functions within a single device

reducing the need of multiple discrete

ises because inverting also is done in

the in pla only itself only so that's

why no need to have uh uh no need to use

different IC so compact design is

possible next is high integration they

offers a high degree of integration

enabling the design of complex digital

systems on a single chip that is

integration means you are integrating

everything on a single chip and last one

simplified design process the

programmability of um that and and or

array simplifies the design process and

uh this is what is the limitation and

advantages of pla hope the things are

clear to you and uh uh I have explained

it using one example implementation also

so thank you everyone we'll meet in next

session so thank you happy learning