Multistage Amplifier: Design Example

Summary

This script details the design process of a multi-stage transistor amplifier with specific gain and resistance requirements. It begins with a common collector stage followed by a common emitter stage and ends with another common collector stage. The design includes careful selection of resistors and capacitors to ensure DC bias points are maintained, with an emphasis on achieving high input resistance and low output resistance. The script also discusses iterative adjustments to meet the desired gain of negative 50, highlighting the importance of loading factors and the need for an iterative design approach to fine-tune the amplifier's performance.

Takeaways

• 🔬 The script discusses the design of a multi-stage amplifier at the transistor level, involving common collector, common emitter, and another common collector stage.
• 📡 The input signal is fed through a coupling capacitor to a common collector amplifier, also known as an emitter follower, which is the first stage of the amplifier.
• 🔍 Coupling capacitors (Cc1, Cc2, Cc3, C4) are added between stages to prevent DC bias point interference from adjacent stages.
• 🎚 The goal is to design an amplifier with a gain of negative 50, an input resistance greater than 100 kilo ohms, and an output resistance less than 1 kilo ohm.
• 🔧 The common emitter stage is designed with specific resistance values to achieve the desired gain, using a split emitter resistance to meet the gain specification.
• 🔗 The input and output stages are designed as common collector stages with a collector current of 0.5 milliamps for simplicity and consistency.
• 🔄 The input resistance of the amplifier is calculated using the reflection rule and the transistor's parameters, aiming to meet the specification of greater than 100 kilo ohms.
• ⚙️ The output resistance needs to be adjusted to be less than 1 kilo ohm, which requires careful selection of resistor values in the output stage.
• 🔄 The loading factor between stages is calculated to ensure that one stage does not substantially load another, affecting the overall gain of the amplifier.
• 🔄 An iterative design process is necessary, where initial design choices may need to be tweaked based on calculations and specifications.
• 🛠 The design process involves trade-offs, such as maintaining a low output resistance while ensuring the gain remains at the desired level.

Q & A

What is the purpose of the multi-stage amplifier discussed in the script?

The purpose of the multi-stage amplifier is to achieve a high gain with specific input and output resistance characteristics, while maintaining the DC bias point of each stage.

What are the three stages of the amplifier described in the script?

The three stages of the amplifier are a common collector stage (emitter follower), a common emitter stage, and another common collector stage.

Why are coupling capacitors used between the stages of the amplifier?

Coupling capacitors are used between the stages to prevent the DC bias point of one stage from being affected by the adjacent stage, ensuring each stage operates independently.

What is the design goal for the gain of the common emitter stage in the amplifier?

The design goal for the gain of the common emitter stage is a negative gain of 50.

What are the specifications for the input and output resistances of the amplifier stages?

The input resistance should be greater than 100 kilo ohms, and the output resistance should be less than 1 kilo ohm.

How is the emitter resistor chosen in the design of the common emitter stage?

The emitter resistor is chosen to center the output voltage around half of the supply voltage (VCC/2), ensuring that the output voltage is centered for proper biasing.

What is the role of the emitter bypass capacitor (CPE) in the amplifier circuit?

The emitter bypass capacitor (CPE) is used to maintain a high gain without altering the DC bias point of the circuit.

Why are the values of R1 and R2 chosen to be equal in the common collector stages?

R1 and R2 are chosen to be equal to create a parallel combination that approximates the desired resistance value, which is larger than the required input resistance for the stage.

How is the input resistance of the common collector stage calculated?

The input resistance of the common collector stage is calculated using the reflection rule, which involves the parallel combination of R1 and R2 and the internal resistance of the transistor.

What is the significance of the loading factor in the design of multi-stage amplifiers?

The loading factor is significant as it determines the interaction between stages, ensuring that the gain of the overall amplifier is maintained without substantial loading effects from one stage to another.

How can the output resistance of the amplifier be reduced to meet the design specifications?

The output resistance can be reduced by adjusting the values of R1 and R2 in the output stage, choosing lower values to achieve a parallel combination that results in a lower resistance.

What is the iterative process mentioned in the script for designing complex amplifiers?

The iterative process involves initial design, checking if the specifications are met, and then tweaking components as necessary to fine-tune the amplifier's performance while considering trade-offs.

Outlines

00:00

🔬 Designing a Multi-Stage Transistor Amplifier

This paragraph introduces the project of designing a multi-stage amplifier with three stages: common collector, common emitter, and another common collector. The purpose is to build an amplifier with a gain of negative 50, while meeting specific resistance requirements. The design includes coupling capacitors at various points to prevent DC bias point interference between stages. The common emitter stage is detailed with specific resistance values to achieve the desired gain, and an emitter bypass capacitor is mentioned to maintain high gain without affecting the DC bias point.

05:00

🔍 Calculating Input and Output Resistances

The focus of this paragraph is on calculating the input and output resistances for the designed amplifier stages. It discusses the selection of resistor values for the common collector stages to meet the specifications of having an input resistance greater than 100 kilohms and an output resistance less than 1 kilohms. The calculations involve the use of beta reflection rule and the impact of resistors R1 and R2 in determining the input resistance. The paragraph also explains the need to adjust the output stage design to achieve the required low output resistance.

10:02

🛠 Adjusting Stage Resistances for Desired Performance

This paragraph delves into the adjustments made to the output stage to meet the specification of having an output resistance less than 1 kilohms. It explains the significance of the parallel combination of R1 and R2 in the common collector amplifier and how their values affect the output resistance. The speaker opts for lower values of R1 and R2 to achieve the desired output resistance and discusses the calculations involved in determining the input and output resistances for the output stage, emphasizing the need to balance these values with the overall design specifications.

15:02

🔄 Iterative Design Process for Amplifier Optimization

The final paragraph discusses the iterative nature of the amplifier design process. It highlights the need to calculate loading factors between stages to ensure the overall gain is maintained at negative 50 without substantial loading effects. The speaker identifies that the loading factor between the gain stage and the output stage is not ideal and suggests increasing the input resistance of the common emitter stage to improve it. The paragraph concludes with the idea that meeting design specifications often requires going back and forth between design and fine-tuning, taking into account various trade-offs.

Keywords

💡Multi-stage Amplifier

A multi-stage amplifier is a type of electronic amplifier that uses multiple amplification stages to increase the signal strength. It is central to the video's theme as the script discusses the design and implementation of such an amplifier at the transistor level. The script describes a three-stage amplifier consisting of common collector, common emitter, and another common collector stage to achieve a high gain with specific resistance values.

💡Common Collector Amplifier

A common collector amplifier, also known as an emitter follower, is a type of amplifier configuration where the input is applied to the base and the output is taken from the emitter. It is used in the script as the first and last stages of the multi-stage amplifier design to provide high input and output impedances, which are crucial for the overall amplifier's performance.

💡Common Emitter Amplifier

The common emitter amplifier is a configuration where the input is applied to the base, and the output is taken from the collector. It is mentioned in the script as the middle stage of the amplifier design, which is responsible for providing the main voltage gain of the amplifier circuit.

💡Coupling Capacitor

Coupling capacitors are used in amplifiers to block DC signals and allow AC signals to pass through. In the script, coupling capacitors Cc1, Cc2, Cc3, and C4 are mentioned to prevent the DC bias point of one stage from affecting the adjacent stages, ensuring that each stage operates independently of the others.

💡DC Bias Point

The DC bias point refers to the quiescent operating point of a circuit where no input signal is applied. The script discusses the use of coupling capacitors to prevent the DC bias point of one stage from being affected by the adjacent stages, which is essential for the stability and performance of the amplifier.

💡Emitter Follower

An emitter follower is a specific type of common collector amplifier that has a high input impedance and a low output impedance. The script uses this term interchangeably with common collector amplifier, highlighting its role in the first and last stages of the multi-stage amplifier design.

💡Input Resistance

Input resistance, also known as input impedance, is a measure of how much an amplifier resists changes in current at its input. The script emphasizes the need for the input resistance to be greater than 100 kilo ohms, which is achieved by selecting appropriate resistor values for the common collector stages.

💡Output Resistance

Output resistance, or output impedance, is a measure of how much an amplifier resists changes in current at its output. The script discusses the requirement for the output resistance to be less than 1 kilo ohm and how it is calculated for the output stage of the amplifier design.

💡Loading Factor

The loading factor is a measure of how much one stage of an amplifier affects the performance of the previous stage. The script calculates the loading factor between the input stage and the gain stage, and between the gain stage and the output stage, to ensure that the overall gain of the amplifier is not significantly affected by the loading.

💡Emitter Bypass Capacitor

An emitter bypass capacitor is used in common emitter amplifiers to maintain a high gain without affecting the DC bias point. The script mentions this capacitor in the context of the common emitter stage design, where it is used to achieve the desired gain of negative 50.

💡Iterative Process

The iterative process refers to the method of refining a design through multiple cycles of evaluation and adjustment. The script concludes by emphasizing the importance of an iterative approach in amplifier design, where initial design choices are made, specifications are checked, and adjustments are made as necessary to meet the design requirements.

Highlights

Introduction of a multi-stage amplifier design at the transistor level.

Description of the three stages: common collector, common emitter, and another common collector.

Use of coupling capacitors Cc1, Cc2, Cc3, and Cc4 to isolate DC bias points between stages.

Design goal of achieving a gain of negative 50 with specific resistance specifications.

Selection of resistance values for the common emitter amplifier stage to achieve the desired gain.

Explanation of the emitter bypass capacitor's role in maintaining high gain without affecting the DC bias point.

Design of the input stage with a common collector configuration and selection of biasing current.

Calculation of input resistance for the first stage using the reflection rule and transistor parameters.

Design of the output stage with considerations for output resistance to be less than 1 kilo ohm.

Iterative process of selecting resistor values to meet both input and output resistance specifications.

Calculation of loading factors between stages to ensure minimal impact on gain.

Identification of the need to adjust the common emitter amplifier to compensate for loading effects.

Discussion on the trade-offs between meeting resistance specifications and maintaining amplifier gain.

Emphasis on the iterative nature of amplifier design to fine-tune the final result.

Importance of understanding the impact of each stage on the overall amplifier performance.

Final thoughts on the importance of an iterative design process in complex amplifier systems.

Transcripts

hello so now we are actually going to go

ahead and implement a multi stage

amplifier at the transistor level so I

have drawn the three stages that we have

studied common collector common emitter

common collector so you should be able

to identify the first stage obviously

the input signal is being fed through a

coupling capacitor but this first stage

here

that's just a common collector amplifier

or an emitter follower then is followed

by a common emitter stage

and then another common collector stage

at the output

notice that I've added coupling

capacitor C c1 c2 c3 and c4

not just at the input and at the output

but also in between stages and again

those are just so that the DC bias point

of one circuit won't be affected by the

adjacent stage

let's go ahead and design try to design

an amplifier similar to the one the

common emitter amplifier that we

designed with a gain of negative 50 but

with the following specifications that

are mb greater than 100 kilo ohms and

allowed to be less than 1 kilo ohm so

for the game of negative 50 we can just

set up the same resistance values that

we have for our common emitter amplifier

stage previously I'm gonna go ahead and

do that and I haven't really entire

system names I'm just gonna go ahead and

enter values directly we had our work

here was equal to 220 K

this was 20 killer arms 20 kilo ohms if

you remember we had a split the emitter

resistance to get the gain of negative

50 into 350 and 1.65 okay this CPE

capacitor that was the emitter bypass

capacitor so that we will get the high

gain without altering the DC bias point

for the circuit

and now we're going to design the common

collector stages input stage and output

stage to get those characteristics so

this is so far a common emitter stage

with a gain of 50

alright let's go ahead and design the

input stage

and as we have done previously we're

going to select

collector current biasing current and

just for simplicity I'm going to select

0.5 milliamps for all my circuit the

common collectors and the common meter

so collector current of 0.5 milliamps

next I was selecting our emitter

resistor so that my output voltage will

be centered around VCC and so case

or II

so their output

so our e is equal to ve / IC or VCC

halves

/ I see just stand over point five

million

420k

that's my emitter resistor here

next I'm going to choose r1 r2

and just like I did in the previous

example I'm gonna select r1 equals r2

because 400

and that will give me a parallel

combination of r1 and r2 approximately

equal to 200 K which is larger than the

the 100 K that I need for my R in and

other factors that are gonna come into

play but as we shall see this is

actually the determining resistance for

the input resistance is the parallel

combination of r1 and

this was to set baby as we mentioned

before the reality would you choose the

resistors to be equal to each other

VB is going to be sitting at half this

is C divided by 2 or 10 volts and then V

is going to shift down by 0.7 volts but

it's a price that we're going to be

willing to pay for simplicity

all rights in this case then our one

employment with r2 will be equal to 200

kilo so I'm going to enter those values

this is 400 K and 400 K

now we can calculate the input

resistance

our Inn has been equal to r1 in Portland

with r2 in parallel with the resistance

seeing when looking into the base of the

first transistor and so that's going to

be beta times by reflection rule

little re of transistor 1 I'm going to

label the transistors CC q1 q2 and q3 so

little early 1 plus

ari when a label does one since it's

connected to transistor 1 this is equal

to r1 in parallel with r 2 is 200 kilo

ohms in parallel with I'm going to

assume beta to be equal to 100 and our

II 1 is going to be equal to 50 I guess

we haven't calculated it but since we're

going to make all the whites and

collector currents for the 3 circuits

equal to 2 point 5 milliamps all of the

little R is

we're gonna be equal to PT which is 25

millivolts

from temperature divided by point 5

milliamps which is 50 on

and that applies to all three stages so

50 plus 20 K

again 200k in parallel with two gig is

approximately equal to 200 K so we're

meeting our specification that the input

resistance is greater than 100 K now

notice that we want the output

resistance to be less than 1 kilo ohm so

if we just apply probably the same

values for our output stages we had for

the input stage the output resistance is

going to be closer to 2 kilo ohms as we

previously calculated and so we need to

change some values in order to get that

a little bit lower so we're gonna go

ahead and design our output stage fresh

new design

we are going to choose

the same value of IC or five milliamps

I'm going to choose Ari

again to gets the the out

Plus to CELTA points

you

yes perhaps over I see

hangover 2 point 5 mili

or 20 kilos

now I'm going to choose

one or two

to set Phoebe

I'm going to apply the same rule I'm

going to choose R 1 and R 2 to be equal

to each other forcing City and so it's

going to really Center BB and supposed

to be e but I'm going to pick different

values and the reason for that is that

if you recall our out

for this stage was equal to I guess we

should calculate us for the previous

stages well so let me go ahead and do

that are out for this stage is equal to

and again we're looking at the output

resistance at that emitter terminal from

the fourth first transistor which is the

output of the first stage so we have our

e1 in parallel with littler e1 plus one

over beta times the resistance is

connected to the base one of the beta

times the parallel combination of r1 r2

assuming negligible resistance from the

input source

so our y1 is 20k

in parallel with 50-plus

200 K divided by beta which is 100 so

this is 20 kilo ohms in parallel with +

50 + 2 k I'm going to approximate as 2 K

and so around will be approximately

equal to 2 kilo again we just mentioned

these same values will not work for our

output stage because we want an output

resistance to be less than 1 kilowatt so

I'm gonna go ahead and calculate both my

input and output resistance for the

output stage now

resistance with these new values

oh I guess we have any pull values just

yet okay so yeah we were talking about

how we wanted to select our one or two

but notice that the parallel combination

of r1 and r2 play a significant role in

determining the output resistance of the

common collector amplifier and

specifically the help of assistance in

Sabean approximated as r1 in parallel

with r2 divided by beta and so we want

to make sure that that does not exceed

one kilo ohm

in the previous case it was to kill arms

and so if I were to choose half the

values for R 1 and R 2 that will give me

1 kilo ohm so we will go for that or

anything lower I'm gonna go ahead and

choose a little bit lower I'm gonna go

with 100 kilo ohms for r1 and r2

1 equals 2 or 2 equals 100 kilo ohms the

end of the way when I do the parallel

combination that will give me 50 kilo

arms and when I divided by beta it will

make me 500 ohms for the output system

so this means our one entirely without

to sequel to

so calculating my our aim for this stage

once I enter my values this is 100 K 400

K

and 20

this will be a one on imparted without

you in parallel with those fiims our

little re 3 plus the emitter resistance

connected to the third transistor

which is now 50k in parallel with 100

times 50 plus 20 K

and

20 k+ v is approximately 20 k multiplied

times 100 is going to give me 2 gig and

so still the 50k is going to dominate a

parallel combination the iron will be

approximately equal to 50 kilo ohms and

are out will now be our III in parallel

with metal our III plus 1 over beta

our one in planet without

our a3 is 20 K in parallel with 50 plus

50 K divided by beta

so this will be 20 K in parallel with

approximately 50 K divided by a beta of

100 will this give me 500 plus 50 will

be 550 that it's going to dominate the

parallel combination since it's much

smaller than the 20k and so this is

going to be approximately equal to 550

now in order to see whether I have met

my design specifications I will need not

only to look at whether I've met the

input and output resistances which I've

already seen that I have met them fact

my input resistance for the overall

circuit is 200 K and my output

resistance is 550 arms

but we need to figure out whether the

gain is can be considered to be negative

50 and that will be the case if I don't

have substantial loading factors so I

need to calculate the loading factors

between my stages so I'm gonna go ahead

and calculate my loading factor number

one

or the interface between the input stage

and the gain stage which is going to be

my input resistance into the second

stage divided by my output resistance

for my first stage plus the input

resistance into my second stage so

entering values I'll have no time factor

1 is equal to now the input resistance

into my common emitter amplifier we

calculated it earlier for the common

emitter stage and it was 20 kilo ohms so

that will be 20 K divided by the output

resistance for my common collector which

is calculated to be 2 K so 2k plus 20 K

and we can see that since pieces met

that the the output resistance for the

first stage is much lower than the input

resistance for the following stage the

loading will be negligible this

approximately equal to 1 it's actually

49 but close enough to one my loading

factor

for the second interface between gain

stage and output stage will be equal to

our in for the third stage divided by

our out of the second stage plus our in

of the third stage

my input resistance for the common

collector output stage is 50 kilo ohms

we just calculated that so 50 K and my

output resistance for the common emitter

amplifier was equal to RC which is 20 K

[Music]

let's 50k so we can see that here this

is going to be something firmly a

substantially lower than one and the

reason for that is 50k even though it is

larger than 20k it's more than twice the

size of 20k it's not really meeting the

condition that it be an order of

magnitude larger at least and so we

expect that there's going to be

substantial loading in between those two

stages how do we go about fixing that

well now in order to increase the value

of the loading factor making it closer

to one we will need to go ahead and

decrease or excuse me

increase the value of the improve our

system and we can see the input

resistance was approximately equal to r1

in parallel with r2 which was 50 K so if

we wanted to make that higher we will

need to increase the values of r1 and r2

let's imagine we made them 200

under cage will give me an equivalent

parallel combination of 100k now the

that will make my loading factor a

little bit closer to what it needs to be

it will be 100 K divided by 20 K plus

100 K then will drive me to the edge of

my output resistance specification my

opal resistance will be approximately

equal to 1 K which is sort of my spec

you'll be slightly lower but

approximately equal so if I wanted to

still keep my low output resistance and

maintain again of 50 then my next step

will be playing with the common emitter

amplifier and trying to increase its

gain a little bit just so that when I

multiply it times the load in factors I

still get a gain of approximately

negative so this gives you an idea for

how the design of really any amplifier

but especially as they get more complex

it's gonna require a little bit of a

spiraling process an iterative process

were you doing any unoriginal design and

then figure out if it meets the

specifications and then you may need to

go back and tweak little things here and

there keeping in mind your trade-offs to

to fine tune your final result thank