PD Lec 67 - Global and Detail Routing | VLSI | Physical Design

Summary

In this video, we dive into the essential concepts of VLSI routing, covering the various stages involved in physical design. Starting from partitioning and floor planning, we explore the routing stack, power planning, and clock tree synthesis (CTS). The focus then shifts to signal routing, explaining the three main stages: global routing, track assignment, and detailed routing. Emphasis is placed on the use of algorithms like Steiner Tree and Maze for global routing, timing considerations in track assignment, and DRC-aware detailed routing. This tutorial offers a comprehensive overview of routing processes crucial for efficient VLSI design.

Takeaways

• 😀 Partitioning is the first step in physical design, followed by floor planning and standard cell placement.
• 😀 Clock Tree Synthesis (CTS) occurs after placement, but some aspects may be handled earlier in the flow due to complex designs and shrinking technology.
• 😀 Routing is a crucial process in physical design, and it involves different stages: global routing, track assignment, and detailed routing.
• 😀 Power planning is done early, with power stripes coming from the top metal layer to the bottom standard cell rail, and this affects the routing layers.
• 😀 Global routing identifies the routable path and calculates congestion, but it is not DRC (Design Rule Check) aware. It uses algorithms like Steiner tree and maze routing.
• 😀 Manhattan distance is used in global routing for calculating the shortest path, which is different from Cartesian distance.
• 😀 Track assignment is timing-aware but not DRC-aware. It assigns specific tracks to nets based on timing needs, helping to reduce via usage.
• 😀 Detailed routing (or nano routing) is the final stage, where the design is DRC and timing-aware, ensuring compliance with design rules and timing constraints.
• 😀 Filler cells are added during detailed routing to fill any empty spaces in the design, contributing to a uniform layout.
• 😀 Congestion and design blockages are analyzed throughout the routing process, with tools accounting for pre-routes and free routes to avoid overwriting them.

Q & A

What is the role of routing in VLSI design?

Routing in VLSI design is crucial for connecting various components (such as standard cells and macros) with electrical signals. It ensures proper signal transmission, power distribution, and clock synchronization across the entire chip.

What are the main components of a routing stack in VLSI design?

A routing stack consists of multiple metal layers that are used to route signals and power. These layers are organized into horizontal and vertical tracks, with each layer having dedicated functions, such as signal routing, power distribution, or clock routing.

What is the first step in VLSI physical design before routing?

The first step in VLSI physical design before routing is partitioning, where the entire design is divided into smaller sections to make it easier to manage and route.

What happens during the floor planning stage of VLSI design?

During the floor planning stage, the overall layout of the design is defined, determining where different components, such as standard cells and macros, will be placed. This step sets the foundation for subsequent stages like cell placement and routing.

How does clock tree synthesis (CTS) relate to routing?

Clock Tree Synthesis (CTS) is related to routing as it involves creating the clock network, which is an essential part of routing. It ensures that the clock signals are evenly distributed throughout the design, and some tracks used for clock routing may overlap with the signal routing.

What is the difference between global routing and detailed routing?

Global routing is an early stage where the tool identifies possible routable paths for nets and assigns layers, but without considering Design Rule Checks (DRC). Detailed routing, on the other hand, is the final stage where all routing paths are finalized, and DRC checks are performed to ensure design integrity.

Why is global routing not DRC-aware?

Global routing is not DRC-aware because its primary goal is to identify rough paths for nets and assign layers without considering precise design rules. It focuses on congestion awareness and finding the shortest path for each net, whereas detailed routing is where DRC checks are performed.

What is Manhattan distance, and why is it used in global routing?

Manhattan distance is the total distance traveled along horizontal and vertical paths, as opposed to a straight line. It is used in global routing because it better approximates the actual routing path, which must navigate around other components and obstacles in the design.

What is the significance of filler cells in VLSI routing?

Filler cells are inserted into empty spaces in the design to ensure that the layout is complete and to help with routing efficiency. These cells are added before detailed routing and contribute to maintaining the integrity of the design by ensuring uniformity.

What tools and algorithms are used for global routing in VLSI design?

For global routing, tools typically use algorithms like the Steiner tree or maze algorithm to calculate optimal routing paths. These algorithms help determine the most efficient routes for each net, considering the available tracks and congestion in the design.