PD Lec 9 - Timing Library | libs | PD Inputs part-3 | VLSI | Physical Design

Summary

In this lecture, the focus is on understanding the timing library used in VLSI physical design. The standard cell library, which includes predefined logic gates, is essential for synthesis, placement, and routing. The lecture covers the timing view of the library, explaining how delay is calculated based on input transition and output load. It introduces two delay models: the NLD (Non-Linear Delay) model, known for its speed but less accuracy at smaller nodes, and the CCS (Composite Current Source) model, which provides more precision at lower technology nodes but at the cost of larger library sizes and more complex processing.

Takeaways

• 😀 A timing library is essential for VLSI physical design, containing data on propagation delays, input transitions, and output load capacitance.
• 😀 Standard cell libraries provide well-defined logic gates used to implement a logical design and are characterized by timing and physical views.
• 😀 The timing view of a standard cell library focuses on timing characteristics like delay and capacitance, crucial for calculating logic path delays.
• 😀 Timing libraries are provided in liberty format, with cell definitions, pin attributes, and delay data organized for EDA tool processing.
• 😀 The Non-Linear Delay Model (NLD) is commonly used for delay calculations in larger nodes but is less accurate for submicron designs due to missing finer details like Miller capacitance.
• 😀 NLD uses a lookup table for delay calculation, where the input transition and output load capacitance are the primary factors in determining delay.
• 😀 The Composite Current Source (CCS) model is more accurate for submicron technologies, accounting for time-varying delays and the impact of Miller capacitance.
• 😀 CCS model introduces an additional parameter—time—that enhances the granularity of delay calculations, making it more accurate at smaller technology nodes.
• 😀 CCS models result in larger library sizes and require more processing power due to the complexity of its time-dependent delay calculations.
• 😀 NLD is fast and efficient for large-node designs, but CCS provides better accuracy at lower nodes, especially for designs where input and output impedances are small.
• 😀 The lecture is part of a VLSI physical design course, and the next session will explore the physical view of standard cell libraries.

Q & A

What is the focus of this lecture in the VLSI Academy series?

This lecture focuses on explaining the timing view of a standard cell library in VLSI design, discussing timing data, delay models, and how they are used in the design process.

What is a standard cell library in VLSI design?

A standard cell library is a collection of predefined and characterized logic gates that can be used to implement a logical design in VLSI. These cells are designed to meet specific requirements for synthesis, placement, and routing algorithms.

What are the two main categories of information included in a standard cell library?

The two main categories of information in a standard cell library are the physical view and the timing view. This lecture discusses the timing view, which includes propagation delay, output load capacitance, and input transition time.

How is delay calculated in a standard cell library?

Delay is calculated based on two primary factors: input transition (the time it takes for the input signal to change state) and output load (the capacitance that the output must drive). The tool calculates the delay by considering both of these factors.

What is the Liberty format in a standard cell library?

The Liberty format is a text-based format used to specify the timing and physical data for standard cells in VLSI design. It includes definitions for cells, pins, and associated timing data required for EDA tools to simulate and optimize the design.

What are the two commonly used delay models in standard cell libraries?

The two commonly used delay models in standard cell libraries are the Non-Linear Delay Model (NLD) and the Composite Current Source Model (CCS). These models are used to calculate propagation delay based on different factors.

What is the key advantage and disadvantage of the Non-Linear Delay Model (NLD)?

The main advantage of the NLD model is that it offers fast delay calculations. The disadvantage is that it loses accuracy at technology nodes smaller than 130 nm, making it less effective for deep submicron designs.

How does the CCS model differ from the NLD model?

The CCS model provides more accurate results for smaller technology nodes, especially below 130 nm, by considering additional factors like Miller capacitance. Unlike NLD, CCS also incorporates time as a variable, making it more precise but resulting in larger library sizes.

Why is the CCS model more accurate at lower technology nodes?

The CCS model is more accurate at lower technology nodes because it accounts for the Miller effect, which becomes significant in deep submicron designs. It also includes time-dependent factors in delay calculations, improving precision at these smaller nodes.

What are the trade-offs associated with using the CCS model over the NLD model?

The trade-offs of using the CCS model include larger library sizes and more complex processing. While it provides better accuracy at smaller technology nodes, the increased size of the library can slow down the loading and processing times in EDA tools.