13.2.2 ALU Instructions

Summary

This script outlines the process of executing ALU instructions with two register operands in a computer's datapath logic. It details the five steps: Fetch, Decode, Read, Execute, and Write-back, emphasizing the role of the program counter, register file, and ALU. The script explains how the system's clock dictates instruction execution frequency and introduces the concept of sign-extension for constant operands. It highlights the simplicity of a reduced-instruction set computer architecture, showing the straightforward datapath logic required for most Beta ISA instructions.

Takeaways

• 📚 The script discusses the datapath logic for executing ALU instructions with two register operands in a computer system.
• 🔍 The process involves five main steps: Fetch, Decode, Read, Execute, and Write-back, which are fundamental to instruction execution.
• 💾 During Fetch, the instruction is read from the main memory location specified by the program counter (PC).
• 🔑 In Decode, the opcode field of the instruction is used to determine the values for the datapath control signals.
• 📝 The Read step involves reading the contents of the registers specified by the RA and RB fields of the instruction.
• 🔧 Execute is where the actual operation, as determined by the ALU, is performed on the two operand values.
• 🔄 The next value for the PC is computed to prepare for the next instruction cycle.
• ⏱ The system's clock signal synchronizes the register file and the PC register, writing new values at the rising edge of the clock.
• 🔢 The clock frequency indicates the rate of instruction execution; for example, a 10ns clock period corresponds to a 100 MHz frequency and 100 MIPS.
• 🛠️ The datapath includes components like an adder for PC+4 computation, a MUX for selecting the initial PC value, and a ROM for control logic based on opcodes.
• 🔄 ALU instructions can use either two register operands or a register and a sign-extended constant, which is selected by a BSEL control signal.
• 📉 The script highlights the simplicity of the datapath logic in a reduced-instruction set computer (RISC) architecture, which is efficient for executing most instructions.

Q & A

What are the main steps involved in executing ALU instructions with two register operands?

The main steps are Fetch, Decode, Read, Execute, and Write-back. Fetch involves reading the instruction from main memory. Decode determines the control signals using the opcode field. Read gets the register contents specified by RA and RB. Execute performs the operation on the operands. Write-back writes the result to the register file.

What is the role of the program counter (PC) in the Fetch step?

The program counter (PC) specifies the location in main memory from where the 32-bit encoded instruction is read during the Fetch step.

How does the Decode step determine the values for the datapath control signals?

In the Decode step, the opcode field (instruction bits [31:26]) is used to determine the values for the datapath control signals.

What is the purpose of the Read step in the execution of ALU instructions?

The Read step involves reading the contents of the registers specified by the RA and RB fields from the register file to provide the operands for the Execute step.

What is the significance of the Execute step in the datapath logic?

The Execute step is where the actual operation, as determined by the control signals, is performed on the two operand values obtained from the register file.

What does the Write-back step entail?

The Write-back step involves writing the result of the operation, which is computed during the Execute phase, to the register file in the register specified by the RC field.

How does the system's clock signal influence the execution of instructions?

The system's clock signal is connected to the register file and the PC register. At the rising edge of the clock, the new values computed during the Execute phase are written to these registers, marking the end of execution for the current instruction and the beginning of the next.

What is the relationship between the clock frequency and the rate of instruction execution?

The clock frequency indicates the rate at which instructions are executed. For example, if the clock period is 10ns, the frequency would be 100 MHz, and the system would execute 100 million instructions per second (100 MIPS).

How is the next value for the PC determined for ALU instructions?

For ALU instructions, the address of the next instruction is simply the address of the current instruction plus 4. This computation is performed by a dedicated adder, and the result is used as the next value of the PC.

What is the purpose of the MUX in the context of the RESET signal?

The MUX is used to select the initial value for the PC when the RESET signal is 1, allowing the system to start execution from a predefined location.

How is the ALU function determined for executing ALU instructions?

The ALU function is determined by the control logic, which in this case is implemented using a read-only memory (ROM). The opcode bits are used as the ROM's address, and the ROM's outputs are the control signals that tell the ALU what operation to perform.

What is the role of the WERF (write-enable register file) control signal?

The WERF control signal determines whether the write operation to the register file is enabled. It should have the value 1 when the result of the ALU operation needs to be written into the RC register.

How is the sign-extension of a 16-bit constant performed in the datapath?

Sign-extension is performed by replicating the high-order bit (ID[15]) of the 16-bit constant sixteen times to form a 32-bit operand. This is achieved through wiring without the need for additional logic gates.

What is the significance of the BSEL control signal in the datapath?

The BSEL control signal selects the second operand for the ALU. When BSEL is 0, the output of the register file is selected, and when BSEL is 1, the sign-extended constant is selected as the operand.

Outlines

00:00

🔍 ALU Instruction Execution Process

This paragraph outlines the process of executing ALU instructions with two register operands, detailing the five main steps: Fetch, Decode, Read, Execute, and Write-back. The Fetch step involves reading a 32-bit instruction from the main memory using the program counter (PC). The Decode step uses the opcode to determine datapath control signals. During Read, register file contents specified by RA and RB are accessed. The Execute step performs the operation on the operands. The PC's next value computation is also discussed. Write-back writes the operation result into the register file. The paragraph emphasizes the importance of the system clock for synchronization and the execution rate, which is determined by the clock frequency. It also includes a sketch of the hardware for Fetch and Decode, explaining the PC's role in instruction fetching and the use of a dedicated adder for 'PC+4' computation. A MUX for the initial PC value during RESET is mentioned. The Decode step's logic computation from the opcode field and the use of a ROM for control signals are also covered. The paragraph concludes with the ALU's function and the significance of the WERF control signal in the Write-back step.

05:00

📚 Datapath Logic for ALU Instructions with Constants

The second paragraph focuses on the datapath logic required for executing ALU instructions that use a constant as the second operand. It describes how a 32-bit operand is formed by sign-extending a 16-bit two's complement constant from the instruction's literal field. A MUX is introduced to the datapath to select between the register file output and the sign-extended constant based on the BSEL control signal. The paragraph explains that no additional logic gates are needed for sign-extension, as it is achieved through wiring. It also touches on the execution flow for ALU-with-constant instructions, noting the control logic's role in setting the BSEL signal and generating the correct ALU function code. The output of the ALU is then written back to the register file, similar to the process described in the first paragraph. The paragraph concludes by highlighting the efficiency of the reduced-instruction set computer architecture, which allows for a straightforward datapath logic capable of executing most instructions in the Beta ISA.

Keywords

💡Datapath

The datapath is the part of a computer's central processing unit (CPU) that performs the actual data manipulation specified by the instruction set. In the context of the video, the datapath logic is essential for executing ALU instructions with two register operands. It includes various steps such as fetch, decode, read, execute, and write-back, which are fundamental to the operation of the CPU.

💡ALU (Arithmetic Logic Unit)

An Arithmetic Logic Unit is a component of a computer's CPU that performs arithmetic and logical operations. The script discusses the necessity of ALU for executing operations on operand values. The ALU is central to the datapath's execution phase, where it carries out the operations determined by the control signals.

💡Program Counter (PC)

The Program Counter is a register that stores the address of the next instruction to be executed by the CPU. In the script, it is mentioned that during the fetch step, the PC provides the location from which the 32-bit encoded instruction is read from main memory, and the next value for PC is computed to point to the subsequent instruction.

💡Opcode

An Opcode is a part of an instruction that specifies the operation to be performed. The script explains that during the decode step, the opcode field (instruction bits [31:26]) is used to determine the values for the datapath control signals, which dictates the operation to be executed by the ALU.

💡Register File

A Register File is a portion of the CPU that holds registers, which are small, fast storage locations within the processor. The script describes how the register file's contents are read during the read step and how the results of ALU operations are written back to it during the write-back step.

💡Control Signals

Control signals are used to manage the flow of data within the CPU and to determine the operation of various components. The script mentions that the control signals for the datapath are derived from the opcode field and are essential for directing the ALU to perform the correct operation.

💡Clock Signal

A Clock Signal is an electrical signal that regulates the operation of the CPU by coordinating the timing of events. The script explains that the system's clock signal is connected to the register file and the PC, and it dictates when new values are written to these components at the rising edge of the clock.

💡Instruction Cycle

An Instruction Cycle refers to the process of fetching, decoding, executing, and writing back an instruction within a CPU. The script outlines the five steps of an instruction cycle, which must be completed for each instruction to be executed properly.

💡MIPS (Million Instructions Per Second)

MIPS is a measure of a computer's processing speed, indicating how many million instructions a CPU can execute in one second. The script uses the example of a clock period of 10ns to illustrate that a 100 MHz clock frequency would result in a processing speed of 100 MIPS.

💡MUX (Multiplexer)

A Multiplexer, or MUX, is a device that selects one of many input signals and forwards the selected input into a single output line. In the script, a MUX is used to select the initial value for the PC when the RESET signal is active, and to choose between the register file output and the sign-extended constant as the ALU operand.

💡Sign Extension

Sign Extension is the process of converting a number from a smaller bit size to a larger one by replicating the sign bit. The script explains that to form a 32-bit operand from a 16-bit constant, the high-order bit is replicated sixteen times, which is a crucial step for ALU instructions using a constant as an operand.

Highlights

Task involves creating datapath logic for ALU instructions using two register operands.

Instructions follow a 5-step process: Fetch, Decode, Read, Execute, and Write-back.

Program Counter (PC) specifies the location for instruction fetch from main memory.

Decode step determines datapath control signals using the opcode field.

Register file read involves RA and RB fields from the instruction.

Execute step performs the operation on operand values.

PC's next value computation is necessary for instruction flow.

Write-back phase writes operation result to the register file.

System's clock signal synchronizes register file and PC register updates.

Clock frequency dictates the rate of instruction execution.

Fetch and Decode steps involve routing PC value to main memory and preparing for instruction bits availability.

Control logic computes values from opcode bits for datapath signals.

ALU operation is determined by ALUFN control signals derived from opcode.

ROM can be used to implement control logic for ALU operations.

ALU output is directed to the register file for the Write-back step.

WERF control signal enables writing into the register file.

Datapath logic for ALU instructions is straightforward in a reduced-instruction set computer architecture.

ALU instructions with a constant operand use a sign-extended 16-bit constant.

MUX is used to select between register file output and sign-extended constant.

Sign-extension is achieved through wiring without additional logic gates.

Datapath is capable of executing most of the Beta ISA instructions after memory and branch instructions are implemented.

Transcripts

Our first task is to work on the datapath logic needed to execute ALU instructions with

two register operands.

Each instruction requires the same processing steps:

Fetch, where the 32-bit encoded instruction is read from main memory from the location

specified by the program counter (PC).

Decode, where the opcode field (instruction bits [31:26]) is used to determine the values

for the datapath control signals.

Read, where the contents of the registers specified by the RA and RB fields (instruction

bits [20:16] and [15:11]) are read from the register file.

Execute, where the requested operation is performed on the two operand values.

We'll also need to compute the next value for the PC.

And Write-back, where the result of the operation is written to the register file in the register

specified by the RC field (instruction bits [25:21]).

The system's clock signal is connected to the register file and the PC register.

At the rising edge of the clock, the new values computed during the Execute phase are written

to these registers.

The rising clock edge thus marks the end of execution for the current instruction and

the beginning of execution for the next instruction.

The period of the clock, i.e., the time between rising clock edges, needs to be long enough

to accommodate the cumulative propagation delay of the logic that implements the 5 steps

described here.

Since one instruction is executed each clock cycle, the frequency of the clock tells us

the rate at which instructions are executed.

If the clock period was 10ns, the clock frequency would be 100 MHz and our Beta would be executing

instructions at 100 MIPS!

Here's a sketch showing the hardware needed for the Fetch and Decode steps.

The current value of the PC register is routed to main memory as the address of the instruction

to be fetched.

For ALU instructions, the address of the next instruction is simply the address of the current

instruction plus 4.

There's an adder dedicated to performing the "PC+4" computation and that value is routed

back to be used as the next value of the PC.

We've also included a MUX used to select the initial value for the PC when the RESET signal

is 1.

After the memory propagation delay, the instruction bits (ID[31:0]) are available and the processing

steps can begin.

Some of the instruction fields can be used directly as-is.

To determine the values for other control signals, we'll need some logic that computes

their values from the bits of the opcode field.

Now let's fill in the datapath logic needed to execute ALU instructions with two register

operands.

The instruction bits for the 5-bit RA, RB and RC fields can be connected directly to

the appropriate address inputs of the register file.

The RA and RB fields supply the addresses for the two read ports and the RC field supplies

the address for the write port.

The outputs of the read data ports are routed to the inputs of the ALU to serve as the two

operands.

The ALUFN control signals tell the ALU what operation to perform.

These control signals are determined by the control logic from the 6-bit opcode field.

For specificity, let's assume that the control logic is implemented using a read-only memory

(ROM), where the opcode bits are used as the ROM's address and the ROM's outputs are the

control signals.

Since there are 6 opcode bits, we'll need 2^6 = 64 locations in the ROM.

We'll program the contents of the ROM to supply the correct control signal values for each

of the 64 possible opcodes.

The output of the ALU is routed back to the write data port of the register file, to be

written into the RC register at the end of the cycle.

We'll need another control signal, WERF ("write-enable register file"), that should have the value

1 when we want to write into the RC register.

Let me introduce you to Werf, the 6.004 mascot, who, of course, is named after her favorite

control signal, which she's constantly mentioning.

Let's follow the flow of data as we execute the ALU instruction.

After the instruction has been fetched, supplying the RA and RB instruction fields, the RA and

RB register values appear on the read data ports of the register file.

The control logic has decoded the opcode bits and supplied the appropriate ALU function

code.

You can find a listing of the possible function codes in the upper right-hand corner of the

Beta Diagram handout.

The result of the ALU's computation is sent back to the register file to be written into

the RC register.

Of course, we'll need to set WERF to 1 to enable the write.

5.oo Here we see one of the major advantages of a reduced-instruction set computer architecture:

the datapath logic required for execution is very straightforward!

The other form of ALU instructions uses a constant as the second ALU operand.

The 32-bit operand is formed by sign-extending the 16-bit two's complement constant stored

in the literal field (bits [15:0]) of the instruction.

In order to select the sign-extended constant as the second operand, we added a MUX to the

datapath.

When its BSEL control signal is 0, the output of the register file is selected as the operand.

When BSEL is 1, the sign-extended constant is selected as the operand.

The rest of the datapath logic is the same as before.

Note that no logic gates are needed to perform sign-extension - it's all done with wiring!

To sign-extend a two's complement number, we just need to replicate the high-order,

or sign, bit as many times as necessary.

You might find it useful to review the discussion of two's complement in Lecture 1 of Part 1

of the course.

So to form a 32-bit operand from a 16-bit constant, we just replicate it's high-order

bit (ID[15]) sixteen times as we make the connection to the BSEL MUX.

During execution of ALU-with-constant instructions, the flow of data is much as it was before.

The one difference is that the control logic sets the BSEL control signal to 1, selecting

the sign-extended constant as the second ALU operand.

As before, the control logic generates the appropriate ALU function code and the output

of the ALU is routed to the register file to be written back to the RC register.

Amazingly, this datapath is sufficient to execute most of the instructions in the Beta

ISA!

We just have the memory and branch instruction left to implement.

That's our next task.