RISC vs CISC | RISC | Reduced Instruction Set Computer | CISC | Complex Instruction Set Computer

Summary

This video offers a comprehensive comparison between RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) architectures. It explains the fundamental differences in instruction set size, instruction fetch time, and design philosophy. The video clarifies that RISC has a fixed, smaller set of instructions leading to simpler and faster execution, whereas CISC features a larger, more complex set allowing for more compact code. It also touches on aspects like addressing modes, the number of registers, compiler design, and the suitability of each architecture for specific types of operations, concluding with the advantages and disadvantages of both.

Takeaways

• 😀 RISC stands for Reduced Instruction Set Computer and CISC for Complex Instruction Set Computer, highlighting the fundamental difference in the number and complexity of instructions.
• 🔍 RISC has a fixed instruction size, whereas CISC's instruction size varies based on the complexity of the instruction.
• ⏱ In RISC, the instruction fetch time is consistent for all instructions, while in CISC, it varies depending on the instruction's complexity.
• 📚 RISC has a smaller and simpler instruction set compared to CISC, which has a larger and more complex set with a variety of instructions.
• 🔄 RISC is based primarily on register-to-register operations, while CISC includes a wider range of memory-based instructions.
• 📏 RISC has fewer addressing modes due to its focus on register operations, whereas CISC offers more modes due to its memory-based instructions.
• 💪 RISC has more registers within the CPU, as it relies heavily on register-to-register operations, while CISC has fewer due to its reliance on complex instructions.
• 🛠️ Compiler design is simpler for RISC due to its smaller and simpler instruction set, whereas it's more complex for CISC due to its larger and more complex set.
• 📈 RISC results in longer program sizes because simple instructions require more steps to perform tasks, while CISC has shorter programs due to the availability of complex instructions.
• 🔢 The number of operands in RISC is fixed, mainly involving registers, while in CISC, the number of operands varies with the instruction, involving both registers and memory.
• 🔧 RISC uses a hardware control unit due to its fixed and simple instruction set, making it faster, while CISC often uses micro-programmed control units due to the complexity of its instructions.
• 🚀 Execution speed is generally faster in RISC due to efficient pipelining facilitated by fixed instruction size, whereas CISC faces inefficiencies due to variable instruction size and the need for frequent pipeline flushes.

Q & A

What does RISC stand for in computer architecture?

RISC stands for Reduced Instruction Set Computer. It is a design approach that uses a smaller set of simple instructions with a fixed instruction size.

What is the full form of CISC in the context of computer design?

CISC stands for Complex Instruction Set Computer. It features a larger set of complex instructions with varying instruction sizes.

Why is the instruction size fixed in RISC architecture?

The instruction size is fixed in RISC architecture to simplify the design and improve the efficiency of instruction fetching and pipelining.

How does the instruction fetch time differ between RISC and CISC architectures?

In RISC, the instruction fetch time is constant for all instructions due to the fixed instruction size. In CISC, the fetch time varies depending on the complexity of the instruction.

What is the typical size and complexity of the instruction set in RISC and CISC architectures?

The instruction set in RISC is small and simple, while in CISC it is large and complex, with a variety of instructions available.

How does the number of addressing modes compare between RISC and CISC architectures?

RISC architecture has fewer addressing modes, mostly because most instructions are based on registers. CISC, on the other hand, has more addressing modes due to its complexity and variety of instructions involving both registers and memory.

Why does RISC architecture have more registers in the CPU?

RISC architecture has more registers because it relies heavily on register-to-register operations, which simplifies the design and execution of instructions.

What is the typical complexity of compiler design for RISC and CISC architectures?

Compiler design is simpler for RISC due to its small and simple instruction set. For CISC, compiler design is more complex due to the large and complex instruction set and the variety of addressing modes.

Why is the program size typically longer in RISC architecture compared to CISC?

The program size is longer in RISC because its simple instructions require more steps to perform complex tasks, whereas CISC can perform the same tasks with fewer, more complex instructions.

How does the number of operands in instructions differ between RISC and CISC architectures?

In RISC, the number of operands is typically fixed, often involving registers and memory. In CISC, the number of operands can vary depending on the instruction, which can involve a mix of registers and memory.

What is the typical control unit design for RISC and CISC architectures?

RISC typically uses a hardware control unit due to its fixed and simple instruction set, which allows for direct execution. CISC often uses a micro-program-controlled unit due to the complexity of its instruction set, which requires more elaborate control mechanisms.

Why is execution speed generally faster in RISC compared to CISC?

Execution speed is faster in RISC because of the uniform instruction size, which allows for efficient pipelining. In CISC, the variable instruction size can lead to inefficient pipelining and the need to flush the pipeline more frequently, slowing down execution.

Which type of operations are RISC and CISC architectures more suitable for?

RISC is more suitable for dedicated operations due to its fixed and simple instructions, while CISC is more suitable for a variety of operations due to its complex instructions that can handle different tasks more efficiently.

Outlines

00:00

🤖 Introduction to RISC and CISC Architectures

This paragraph introduces the concepts of Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC) architectures. The speaker explains that RISC has fewer and simpler instructions, while CISC features a larger set of complex instructions. The video promises to delve into the design philosophies and differences between the two, providing insights into instruction size, fetch time, set size, addressing modes, and the number of registers involved. It sets the stage for a comprehensive comparison based on various parameters.

05:02

🔍 Deep Dive into RISC and CISC Characteristics

The second paragraph delves deeper into the characteristics of RISC and CISC architectures. It discusses the simplicity and fixed instruction size of RISC, which leads to a smaller and simpler instruction set, fewer addressing modes, and a higher number of registers within the CPU. In contrast, CISC is characterized by its variable instruction size, larger and more complex instruction set, a greater variety of addressing modes, and fewer registers due to its reliance on complex instructions. The paragraph also touches on compiler design, program size, code density, the number of operands, control unit complexity, execution speed, and the suitability of each architecture for specific types of operations. It concludes with the advantages of RISC in pipelining and its suitability for dedicated operations, whereas CISC is better for varied operations due to its complex instruction set.

Keywords

💡RISC

RISC stands for Reduced Instruction Set Computer. It is a type of microprocessor architecture that utilizes a small, highly optimized set of instructions. In the video, it is emphasized that RISC has fewer instructions compared to CISC, leading to simpler and faster execution, ideal for dedicated operations.

💡CISC

CISC stands for Complex Instruction Set Computer. This architecture includes a large set of instructions, allowing more complex operations to be performed with fewer lines of assembly code. The video contrasts CISC with RISC, noting that CISC's complex instructions and multiple addressing modes make it suitable for a variety of operations.

💡Instruction Set

An instruction set is the collection of instructions that a CPU can execute. In the video, the RISC instruction set is described as small and simple, while the CISC instruction set is larger and more complex, impacting the design and functionality of the processors.

💡Instruction Size

Instruction size refers to the length of the instructions in bits. The video explains that RISC instructions have a fixed size, leading to uniformity in execution time, while CISC instructions vary in size depending on their complexity, affecting fetch time and pipeline efficiency.

💡Instruction Fetch Time

Instruction fetch time is the time it takes to retrieve an instruction from memory. The video highlights that RISC fetch time is constant due to fixed instruction size, whereas CISC fetch time varies with instruction complexity, impacting overall performance.

💡Addressing Modes

Addressing modes are the ways in which the operand of an instruction is specified. RISC has fewer addressing modes because it mainly operates with registers, while CISC supports many addressing modes due to its complex instructions, as discussed in the video.

💡Registers

Registers are small, fast storage locations within the CPU. The video notes that RISC architectures have many registers to support their simplified instruction sets, while CISC architectures have fewer registers, relying more on memory operations.

💡Compiler Design

Compiler design refers to the complexity of translating high-level code into machine code. According to the video, RISC compilers are simpler due to the smaller, more uniform instruction set, while CISC compilers are more complex due to the diverse and intricate instruction set.

💡Program Size

Program size is the amount of memory required to store a program. The video explains that RISC programs tend to be longer because of the simpler instructions, while CISC programs are shorter due to their complex instructions that accomplish more in fewer lines.

💡Pipelining

Pipelining is a technique where multiple instruction phases are overlapped. The video states that RISC benefits more from pipelining due to its fixed instruction size, leading to fewer pipeline stalls, while CISC suffers from inefficient pipelining due to variable instruction sizes.

Highlights

Basic comparison between RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) architecture is discussed.

RISC has fewer instructions in the set compared to CISC which has more complex instructions.

Instruction size in RISC is fixed, while it varies in CISC depending on the complexity of the instruction.

RISC has the same instruction fetch time for all instructions, whereas in CISC it varies based on instruction complexity.

RISC's instruction set is small and simple, while CISC's is large and complex with a variety of instructions.

RISC is based on load and store operations, whereas CISC has a variety of complex instructions concerning memory.

RISC has fewer addressing modes due to its reliance on registers, while CISC offers more due to its complexity.

RISC has more registers inside the CPU, as it is based on register execution, while CISC has fewer due to its complexity.

Compiler design is simpler for RISC due to its small set of instructions, while it's complex for CISC.

Program size tends to be longer in RISC due to its simple instructions, while it's shorter in CISC with complex instructions.

RISC has a fixed number of operands, mainly in registers, while CISC has variable operands including memory.

RISC uses a hardware control unit for its fixed and simple instructions, while CISC uses micro-program controlled due to complexity.

RISC offers faster execution speed due to efficient pipelining, while CISC's variable instruction size leads to inefficiencies.

Pipelining is more effective in RISC due to its fixed instruction size, while it's less effective in CISC.

RISC is more suitable for dedicated operations, while CISC is suitable for a variety of operations due to its complex instructions.

The major advantage of CISC is its better code density compared to RISC.

Transcripts

welcome to engineering Funda family in

this video I'll be discussing basic

comparison in between risk and cisk

architecture my dear students risk means

reduced instruction set computer and

cisk means complex instruction set

computer so risk is having less number

of instruction in set of computer and in

cisk you'll be having complex

instruction so there will be many

instruction in set of computer but when

we talk about both of these computers

design then there are many things that

you need to know with respect to

different parameters I'll explain you

each and everything with respect to

different parameter in this video so I

can give you guarantee after watching

this video you'll be having exit idea

about what is risk what is cisk and how

design philosophy is there behind risk

and cisk so my dear students here when

we talk about risk and cisk then first

of all you should know what what is the

basic full form which is there with risk

it is reduced instructions at computer

and cisk is complex instruction set

computer so with risk you'll be having

less number of instruction in computer

and with cisk you'll be having many

instruction along with complex

instruction in computer Here My Dear

students you should know instruction

size with risk it is fixed right while

with cisk it varies with respect to

instruction for complex instruction size

of instruction will be more and for

simple instruction size of instruction

will be less right so Here My Dear

students size of instruction varies with

respect to operation in CIS but it is

almost fixed with all the instructions

with risk Right Here My Dear students

instruction fetch time that is also same

for all the instruction with risk but

instruction fetch time that varies with

respect to instruction in cisk as if you

have complex instruction in that case

you need to have more instruction fetch

time and for simple instruction it will

take less time to fetch the instruction

right so based on complexity instruction

fetch time that is even changing with

respect to cisk architecture while with

risk you'll be observing it is Con

instant for almost all the instructions

Right Here My Dear students when we talk

about instruction set then it will be

small and simple for risk right but with

cisk it will be large and complex there

are varieties of instructions will be

available right there will be more

memory kind of instructions that will be

available with cisk with risk

instruction set that will be purely

based on resistors only right as risk is

there based on load and store and and

CIS is not there based on load and store

right so as cisk is not there based on

load and store varieties of complex

instructions are available with respect

to memory but risk architecture that is

there based on resistors only right so

small and simple instructions will be

there with risk architecture my dear

students addressing modes will be less

with risk architecture why the reason is

most of the instructions are based on

resistors only right so less addressing

modes will be there and here with cisk

many addressing modes will be there why

the reason is cisk architecture is

having instructions based on resistors

as well as memory so when you operate

with varieties of modes with respect to

memory you'll be having many other modes

while with risk we don't have many modes

with respect to memory right we just

have load and store mode with respect to

memory so less number of modes will be

there in terms of addressing mode and

CIS is having more addressing mode right

my dear students when we talk about

number of resistors then risk will be

having many resistors inside CPU while

with CIS it will be having few resistors

why the reason is risk architecture that

is based on resistors execution only and

CIS architecture that is based on

complexity of instructions right so here

you don't need to have many resistors

you will be operating with memory right

so inside memory you can store the data

and you can operate along with

instructions while with risk you'll be

performing almost all the operations

with respect to resistors so you should

have many resistors in Risk architecture

Right Here My Dear students when we talk

about design of compiler then it will be

simple with risk why the reason is we

have small set of instructions right and

when we talk about cisk architecture its

compiler design will be complex why the

reason is instruction set is complex

many addressing modes are there so your

compiler design will be complex with

cisk

architecture Here My Dear students when

we talk about program size then it will

be long with risk architecture why the

reason is we have simple instructions it

is based on resistors only right so to

perform any particular task you'll have

to write many instructions so your

program size will be long in cisk we'll

be having small program why the reason

is we are having complex instructions

right and because of complex

instructions are available by writing

few instructions only we can perform

program right so you'll be observing

risk architecture is having weak code

density with respect to program and CIS

architecture that is having better code

density better code density means less

number of instructions are there in

given program right while with risk

you'll be having more instructions for

same program that's why we code density

will be there my dear students when we

talk about number of operants then that

is fixed with risk architecture mainly

it will be there in resistors only why

the reason is most of the instructions

are there with respect to resistors only

and load and store is happening with

risk architecture right so one operand

that will be resistor only second

operand could be Memory but it will be

having fixed number of operands when we

talk about cisk architecture operants

varies with respect to instructions it

can be resist it can be Memory right so

you'll be observing variable operant are

there for simple instructions you may

have resistors as a operant but for

complex instruction you may be having

resistors as well as memory as a operand

right my dear students when we talk

about control unit then Hardware control

unit is there with risk why the reason

is instruction set is fixed it is having

simple instruction so we can have

hardwire control right but with cisk if

you provide Hardware control then it

will be very costly right so here we

will be having control unit with micro

program controlled right so here

Hardware control that will be faster

compared to micro program controlled

with cisk that you should know right as

Hardware will provide direct execution

in micro program micro program will get

executed and it will control that right

here when we talk about execution speed

then risk is very fast compared to cisk

why the reason is here instruction size

is same because of that you can have

efficient pipelining here instruction

size is different so you can have

inefficient pipelining in pipelining in

parallel we can execute many instruction

here because of inefficient pipelining

you need to flush the pipelining

frequently in that case your execution

will be slower right only major

advantage which is there with CIS that

is better code density compared to risk

that one can say Right Here My Dear

students as I have told you pipelining

is more effective with risk and it will

be less effective with cisk right why

the reason is variable size instruction

will insert bubble in the pipelining and

in Branch execution you'll be observing

that you'll have to flush the pipeline

right so cisk is having more bubbles in

the pipeline risk is having less bubble

in the pipeline that's why risk is

effective in pipelining and my dear

students when we talk about processor

then you should know this risk is more

suitable for dedicated operation and

cisk that is more suitable for varieties

of operation why it is more suitable for

varieties of operation the reason is

complex instructions are there with risk

you have fixed and simple instructions

so you will have to perform dedicated

operation using risk but as if you have

varieties of operation then you should

go for for cisk so that is how risk and

cisk are there and this is how design

philosophy is there I hope it is clear

to you still if any quer is there what I

want is you just post that in comment

box to have discussion with me thank you

so much for watching this video