Breaking Old Chip Physics with New 2D Materials

Summary

A new research from UC Santa Barbara presents a breakthrough in transistor technology, potentially reducing power consumption by 70%. The study explores the use of 2D materials in tunneling Field Effect transistors (TFETs), which require less voltage to operate, significantly lowering the energy barrier for electron flow. This innovation could revolutionize power efficiency in devices from smartphones to AI chips, although challenges in manufacturing and cost remain before widespread adoption.

Takeaways

• 🔋 The script discusses the importance of performance, power consumption, cost, and availability in modern device usage, with a focus on reducing power consumption through transistor innovation.
• 🔧 It highlights the fundamental limits in the physics of transistors, specifically the 60 mV per decade limit that has been a constraint for over 30 years in modern chip designs.
• 🌟 A new research paper from UC Santa Barbara presents breakthrough findings that could significantly lower power consumption in transistor-based devices.
• 📈 The script explains the binary nature of transistor switches and their power cost in turning on and off, with the reality being more analog than digital.
• 🔬 The research introduces a t-FET (tunneling Field Effect transistor) and its use of 2D materials to lower the energy barrier for electron flow, resulting in reduced power requirements.
• 📊 The energy diagram comparison between standard MOSFETs and t-FETs illustrates the reduced energy requirement for electron tunneling in the latter.
• 🚀 The research achieved an 18 mV per decade performance, marking a 70% decrease in the active voltage needed for modern processors, which could benefit a wide range of devices.
• 🛠️ The script mentions that while the technology is promising, it is still in the research phase and not yet ready for mass production or widespread adoption.
• 📉 One of the limitations of the new t-FETs is their significantly slower operation speed compared to finFETs at equivalent voltages.
• ⚡️ However, the t-FETs show extremely low static power consumption, with a billion transistors consuming only 0.22 microwatts, compared to 1.54 watts for finFETs.
• 💡 The potential application of these new transistors in neuromorphic chips is discussed, with the technology showing thousands of times lower power per neuron fired at low activity levels.

Q & A

What are the two main aspects of power consumption in electronic devices?

The two main aspects of power consumption are peak power, which is the power consumed during operation, and idle power, which is the power consumed when the device is not in use.

What is the fundamental limit in the physics of transistors that has been a challenge for over 30 years?

The fundamental limit is the 60 mV per decade voltage requirement for transitioning the electron flow in a standard MOSFET, which contributes significantly to power consumption in modern chips.

What is the significance of the research paper from UC Santa Barbara in the context of transistor design?

The research paper showcases a breakthrough in reducing power consumption by introducing a new design for transistors that lowers the power requirements for turning them on and off.

How do modern computer chips, GPUs, and wafer-scale devices differ in the number of transistors they contain?

Modern computer chips contain millions of transistors, GPUs contain billions, and wafer-scale devices, like the Broadcom Tomahawk 4, can contain trillions of transistors.

What is the role of doping in the creation of a MOSFET?

Doping is a process where silicon atoms are removed or replaced with elements like boron or phosphorus to adjust the structure of the silicon, making it electron-rich or electron-deficient, which is essential for the functioning of a MOSFET.

What is the significance of the energy diagram in understanding electron transport in a transistor?

The energy diagram represents the energy levels of electrons, showing how the energy barrier is reduced by applying voltage to allow electrons to flow between the source and drain in a transistor.

What is a Tunneling Field Effect Transistor (TFET) and how does it differ from a standard MOSFET?

A TFET is a type of transistor that uses quantum tunneling to allow electrons to move from one end of the transistor to the other without a physical path. It differs from a standard MOSFET by doping the source and drain with opposite polarity, which predisposes the flow of electrons but requires a lower voltage to enable tunneling.

What is the key advantage of using 2D materials in the TFET design presented in the research paper?

The key advantage is that the 2D materials used in the TFET design allow for a significant reduction in the voltage required for electron tunneling, achieving an 18 mV per decade performance, which is a 70% decrease compared to the standard 60 mV per decade in MOSFETs.

How does the new TFET design impact the power consumption of neuromorphic chips?

The new TFET design, when modeled as part of a digital neuromorphic chip, showed a power consumption that is several thousand times lower per neuron fired at low activity, making it highly efficient for low-power applications.

What are some of the barriers to high-volume adoption of the new TFET technology presented in the research paper?

Some barriers include the specialized manufacturing techniques required for 2D materials, which are not yet standardized for mass production, and the higher cost associated with low-volume production compared to the optimized processes of current technologies.

Outlines

00:00

🔋 Transistor Power Consumption and Design

This paragraph discusses the importance of performance and power consumption in modern electronic devices, emphasizing the cost and availability of these technologies. It explains the concept of peak and idle power consumption, which are dependent on the voltage required to switch transistors between states. The script introduces a research paper from UC Santa Barbara that aims to reduce power consumption in transistors. It also touches on the limitations of current transistor design, known as MOSFETs, and the fundamental physics involved in their operation. The paragraph concludes with an introduction to the concept of energy diagrams and the potential for new research to overcome the 60 mV per decade limit that has been a constant in chip design for over 30 years.

05:01

🌐 Tunneling FETs and 2D Materials for Power Efficiency

The second paragraph delves into the specifics of tunneling Field Effect transistors (TFETs), which are a type of transistor that allows for electrons to move between states through quantum tunneling, rather than thermal diffusion. It explains how TFETs work with a different doping process that creates an electron-rich and electron-deficient environment within the transistor, facilitating the tunneling effect. The paragraph highlights the research's use of a 2D channel material, which has enabled a significant reduction in the voltage required for electron transition, from 60 mV per decade to 18 mV per decade, a 70% decrease. This advancement could lead to substantial improvements in power efficiency across various devices, from AI chips to smartphones. The script also discusses the potential and current limitations of 2D materials in manufacturing, including the challenges of scaling and cost.

10:02

🚀 The Future of Transistors and Neuromorphic Chips

The final paragraph reflects on the potential impact of the new transistor technology on the future of computing, particularly in the area of neuromorphic chips, which are designed to mimic the neural structure of the human brain. It mentions a comparison between the new 2D TFET technology and current finFET devices, showing a significant reduction in power consumption, albeit with a trade-off in speed. The script also discusses the barriers to widespread adoption of this technology, including manufacturing challenges and cost. It concludes with a broader perspective on the evolution of transistor technology and the importance of revisiting and rebuilding the foundations of chip architecture to continue advancing the field.

Keywords

💡Transistor

A transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is the fundamental building block of modern electronic devices. In the video's context, it is central to the discussion of power consumption and performance in silicon chips, with the script mentioning the billions of transistors in a GPU and the trillions in a Broadcom Tomahawk 4 chip.

💡Power Consumption

Power consumption refers to the amount of electrical energy used by an electronic device or a component over time. The video emphasizes the importance of reducing power consumption, particularly in the context of transistors, by discussing the peak power and idle power, and how they relate to voltage requirements for switching transistors on and off.

💡MOSFET

MOSFET stands for Metal-Oxide-Semiconductor Field-Effect Transistor. It is a type of transistor commonly used in modern electronics. The script explains that MOSFETs have a '60 mV per decade' limit, which is a fundamental restriction on the voltage needed to turn the transistor on or off, affecting power efficiency.

💡Doping

Doping is the process of adding impurities to a semiconductor material to change its electrical properties. In the script, it is mentioned that the source and drain of a MOSFET are doped with elements like boron or phosphorus to adjust the silicon's electron richness or deficiency, which is crucial for the transistor's operation.

💡Voltage

Voltage is the electric potential difference between two points. The video discusses how voltage is applied to create an electric field that facilitates the flow of electrons in a transistor. It is also highlighted as a key factor in the power consumption of chips, with the '60 mV per decade' limit being a critical voltage-related concept.

💡Tunneling FET

A Tunneling Field-Effect Transistor (TFET) is a type of transistor that uses quantum tunneling of electrons to switch between states. The script introduces this technology as a means to reduce power consumption, with the TFET being easier to turn on and off, thereby requiring less power.

💡2D Material

2D materials are materials that are only a few atoms thick and exist in a single plane, such as graphene. In the video, 2D materials like molybdenum disulfide (MoS2) and tungsten diselenide (WSe2) are mentioned as being used in the channel and source of the TFET, which helps achieve a lower '18 mV per decade' performance, significantly reducing power requirements.

💡Quantum Tunneling

Quantum tunneling is a quantum mechanical phenomenon where particles move through a potential barrier, even when they do not have enough energy to surpass it classically. The script explains that TFETs exploit this effect to allow electrons to move from the source to the drain without a physical path, which requires less energy and thus less power.

💡Neuromorphic Chip

A neuromorphic chip is a type of computer chip designed to mimic the neural structure of the human brain. The video discusses how the new 2D TFET technology was modeled as part of a digital neuromorphic chip, highlighting its potential for extremely low power consumption, which is crucial for such chips.

💡Manufacturing Methods

Manufacturing methods refer to the processes used to produce electronic components. The script points out that while the new transistor technology is promising, there are challenges in adopting it at scale due to specialized manufacturing techniques required for 2D materials, which are not yet optimized for high-volume production.

💡Cost

Cost is a critical factor in the adoption of new technologies. The video mentions that the cost of manufacturing the new type of transistors with 2D materials is currently higher due to low volume production and the need for specialized manufacturing techniques, which is a barrier to widespread adoption.

Highlights

New research from UC Santa Barbara aims to reduce power consumption in transistor-based devices.

The power consumption of transistors is tied to the voltage needed to flip the state of the transistors from 0 to 1.

A fundamental limit in physics has restricted the power efficiency of transistors for over 30 years, known as the 60 mV per decade limit.

Modern computer chips, GPUs, and other devices use billions to trillions of transistors, each with a power cost when switched.

Transistors work by applying an electric field to allow electron flow, reducing energy barriers through applied voltage.

MOSFETs (Metal Oxide Semiconductor Field Effect transistors) are the current standard for transistors, with a design limited by the 60 mV per decade rule.

UC Santa Barbara researchers have developed a new approach using a tunneling Field Effect transistor (TFET) for lower power consumption.

TFETs work on the principle of quantum tunneling, allowing electrons to move without a physical path by applying a voltage.

The energy required for electron tunneling in TFETs is significantly lower than in standard transistors, offering a 70% decrease in active voltage.

The research introduces a 2D channel material that enables the 18 mV per decade performance, a substantial improvement over the traditional limit.

2D materials, such as transition metal dichalcogenides (TMDs), offer unique properties for transistor design due to their limited Z-direction scaling.

The new TFET design was compared to 7nm FinFET devices, showing a significant reduction in static power consumption.

While the TFET operates at a slower speed, its ultra-low power consumption is ideal for neuromorphic computing applications.

The research paper models the TFET as part of a digital neuromorphic chip, demonstrating its potential for future low-power devices.

There are challenges in manufacturing these new transistors at scale, including specialized techniques for 2D materials.

Cost is a barrier to adoption, as low-volume production of new technology is typically more expensive.

The potential for fundamentally changing the physics of transistors could pave the way for more efficient future hardware.

Transcripts

for most of us who use devices from

day-to-day there are two things that

matter most performance and power beyond

that there's the cost and when exactly

can I get my hands on it the topic of

power often has two main angles the peak

power consumed and the idle power

consumed both of those rely on how much

voltage is needed to convert the

transistors the switches in Silicon

chips inside from a zero to a one and

vice versa despite advances in

manufacturing and packaging there has

been a fundamental limit in the physics

of that 0 to one to zero flip a new

research paper from UC Santa Barbara is

showcasing breakthrough numbers to help

lower the power consumption of anything

with a

transistor what's your minimum

specification so modern computer chip

has millions transistors or in the case

of gpus billions or in the case of wave

scale dinner plates trillions this is

the broad broadcom Tomahawk 4 and this

has billions of transistors each

transistor is a switch and there's a

power cost turning it on and off we

often like to think that a switch is a

binary one or zero in a very digitall

likee context and for the most part it

makes everything we talk about a lot

simpler however the reality is

definitely a bit more analog than that

for this video we're going to talk about

transistor design the physics of of

electrons and there'll be some graphs as

well this is still research but I'll

take you through let's start with what

we need in a switch in a standard

computer chip a switch is enabled by

allowing electrons to flow between two

locations in order to get electrons to

flow we apply an electric field

attracting electrons to flow through a

material it lowers the energy barrier

for those electrons to flow the barrier

is reduced by orders of magnitude due to

this applied voltage and what might be

one in a million chance of an electron

flowing becomes one in one six orders of

magnitude difference the voltage to

create that electric field that causes

the change is where a lot of the power

in modern chips comes from and the key

limit to Modern chip designs which

hasn't changed in over 30 plus years

that limit is given at 60 molts per

order of magnitude also known as 60

molts per decade in order to transition

those six orders of magn itude it

requires around 360 MTS and this is

above and beyond the minimum voltage

required to get the chip to even

function the reason this exists is due

to the fundamental premise of the modern

transistor modern transistors are also

known as mosfets metal oxide

semiconductor Field Effect transistors I

mentioned that we tried to get electrons

to flow between two locations known as a

source and a drain the voltage is

applied through an oxide layer known as

a gate in order to build the transistor

in the device the source and the gate

have silicon atoms removed or replaced

in a process called doping you can dope

with elements like Boron or phosphorus

to adjust the structure of the Silicon

making its electron rich or electron

deficient in a mosfet both source and

drain are doped the same way and then by

applying a voltage to this gate

separated by this oxide it creates a

field that attracts electrons from

source to drain this is a design that

has a 60 molt per decade

limit one way to represent this electron

transport is an energy diagram in this

diagram we have the standard transistor

and the lines indicate the energy level

of the electrons the energy level is

more of a spectrum than a line and in

order to move from source to gate you

have to give the electrons more energy

or reduce the energy requirement to move

between them through what we call the

channel in the case of a mosfet we

reduce the energy barrier of the channel

the new research published in nature by

the research group at UC Santa Barbara

has found a way to make the transistor

easier to turn on and off lowering the

power requirements it involves a t fet

or tunneling Field Effect transistor

which isn't a new technology we'll get

to that in a second but the materials

used are new in order to help drive down

the power in a tunneling fet we build a

transistor in a similar way a source a

channel a drain and then a control gate

with an oxide except this time instead

of doping the source and drain the same

way they are doped with opposite

polarity this means one side of the

transistor is electron rich and the

other side is electron deficient it

means that the transistor is predisposed

to wanting these electrons to flow

however the barrier between them is

either physical with no path or too far

for Quantum tunneling to actually take

place as perhaps name implies tunneling

fets work by applying a vol to the gate

that causes electrons to tunnel from one

end of the transistor to the other this

is a Quantum effect there's no physical

path but we have electrons ready to move

from one side to the

other in order for the electrons to move

we have to talk about the electron

energies again this is the diagram

before where we showed with standard

transistors with that the energy hump to

get over in order for the electrons to

flow due to the way tunneling fets are

manufactured the energy diagram actually

looks like this which might be a little

confusing at first but for those

familiar with the technology terminology

this is a representation of electron

bonding and antibonding orbital energies

also known as the electron bands in

order for tunneling to occur the

electron energies need to overlap such

that the electron can transfer from

source to drain while staying at the

same energy level and conserving energy

when the voltage is applied to the

tunneling fet the energy levels for the

electrons in the source and drain move

from not overlapping to overlapping

enabling this Quantum effect the energy

required to do this is much less than a

standard transistor again we previously

mentioned this 60 molts per decade

number yet in this research paper with

the 2D Channel material used the group

were able to represent it at 18 molts

per decade a 70% decrease reducing the

active voltage for modern processors by

70% would be a sizable Improvement it

anything from Big AI chips down to

smartphones and smart devices let's

cycle back and talk about that channel

material I mentioned it's a 2d material

but what is a 2d material if you take

standard table salt known as sodium

chloride it naturally forms a large

cubic array of sodium ions and chloride

ions the elements used naturally form a

large array almost every combination of

elements outside of organic materials

form large arrays however there are a

few that end up limited with which

directions they can spread 2D materials

fall into this Gap they can scale in an

X and a y direction but due to the

nature of the elements used do not scale

in The Zed Direction one group of two

dimensional materials are called tmds

which is an acronym for transition metal

dialogen the name isn't important but

these are materials you may have heard

me mentioned before in other videos

malum disulfide or mos2 is one and

tungsten diell oride wse2 is another

these both form 2D materials that kind

of look like this it's a sheet and yes

if you know anything about Nano sheets

this is where Nano sheets is going to

end up as well however in this research

paper 2D materials were used for the

channel as well as the source to enable

this 80 Ms per decade performance it was

compared to equivalent 7 nanometer

finfet devices and provided some

surprising results

firstly any device this much in research

isn't going to be ready for prime time

anytime soon regular transistors have

had 50 years of development these new

transistors have not so at an equivalent

voltage where a finfet could run at 1

GHz this tunnel fet would run at 0.7

mahz that's over a thousand times slower

however at that voltage the static power

of a billion transistors is only 0.22

microwatt compared to 1.54 watts of the

finfets that's a factor difference of

over 7 million due to these features the

research paper modeled the transistor as

part of a digital neuromorphic chip and

compared it against known models of

modern neuromorphic chips the research

groups behind this design are actually

involved in neuromorphic research hence

the focus on something super low power

and researchers from Intel's

neuromorphic team were also involved in

this research neuromorphic chip power

consumption is usually measured by an

activity Factor as in how regularly a

neuron is used or fired at low activity

the new 2D tunnel fet showcased several

thousand times lower power per neuron

fired now there are a couple of barriers

to high volume adoption here as you

might expect with any early research

technology even though the paper states

that standard manufacturing methods have

their limitations standard manufacturing

methods are used more often not because

they can scale and create millions of

chips per day the techniques to create

these type of transistors are

specialized especially when using 2D

materials such as the malum disulfide or

tungsten D teleride lots of research is

going on today to even manufacture those

on standard 300 mm Wafers for use with

standard cosos manufacturing methods

another limitation is cost low volume

parts will be higher uh higher cost to

manufacturer and one of the benefits of

the current generation of mass

production technology is that it has had

50 to 70 years of optimization put into

it one of the things I love about what I

do is the ability to look at what's new

what's the latest and greatest it's why

I spent a lot of time talking about the

latest generation of chips for CPUs for

AI or specialist compute it's great that

we can build on the foundational

technologies that we have got to where

we are today however if we can find New

Foundations with less restrictive limits

to help the future evolve faster and the

better and good for all then it's worth

keeping an eye out for potential roots

for better Hardware in my discussions

with legendary chip architect Jim Keller

he is always an advocate for rebuilding

the foundations of an architecture as

often as possible design something good

then get the low hanging fruit in the

Next Generation then start again with a

fresh sheet of paper it allows you to

reset your Baseline time and time again

in land of transistors we're doing that

with PL of transistors to finfets

finfets to Nano ribbons or gate all

around and then in the future we have

Fork sheets and stacked transistors on

that road map as well but fundamentally

changing our physics perhaps we need to

do that sometime soon

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[Laughter]

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