Dynamic Random Access Memory (DRAM). Part 2: Read and Write Cycles

Summary

This video delves into the process of reading and writing data in DRAM. It explains how a memory array is structured, with rows and columns of cells, each holding a binary value. The video covers how address buses, row and column address buffers, and sense amplifiers work together to select a specific memory cell for reading or writing. The step-by-step cycle of reading and writing data is described in detail, emphasizing the timing and operations involved in both processes, including the refreshment of row data and the use of control signals.

Takeaways

• 😀 DRAM consists of millions of cells arranged in a rectangular array, with each cell containing a transistor and a capacitor.
• 😀 A charged capacitor in a DRAM cell represents a binary 1, while an uncharged one represents a binary 0.
• 😀 DRAM arrays are divided into rows and columns, with each cell accessed via horizontal word lines and vertical bit lines.
• 😀 Memory addresses are conveyed using an address bus, and a six-line address bus can uniquely identify each cell in an 8x8 array.
• 😀 The address bus is split into row and column address buffers, which temporarily store the respective addresses.
• 😀 Memory address multiplexing reduces the number of external pins needed, which is essential for large memory systems.
• 😀 DRAM modules typically require pins for row and column address strobes, data, and control signals.
• 😀 A read cycle in DRAM involves precharging bit lines, applying the row address, and using a decoder to select a specific row.
• 😀 During a read cycle, the value in the selected row is latched into sense amplifiers, and the column address is then used to fetch the specific bit.
• 😀 DRAM read cycles are destructive, meaning the content of cells is partially altered during the reading process, but the data is safely restored.
• 😀 A write cycle in DRAM is similar to a read cycle, but involves writing new data into a selected cell after the row and column addresses are applied.

Q & A

What is the basic structure of a DRAM cell?

A DRAM cell is made up of a transistor and a capacitor. The capacitor holds a charge to represent a binary '1' and no charge to represent a binary '0'.

How does a differential sense amplifier function in a DRAM array?

A differential sense amplifier detects the values in an entire row of cells, latches onto them, and writes them back, ensuring that the data is accurately read and stored.

What is the purpose of the address bus in a DRAM system?

The address bus is used to convey the memory address to identify specific cells in the DRAM array. For a 64-cell array, a 6-line address bus is used to uniquely address each cell.

What role do the row and column address buffers play in the memory module?

The row and column address buffers temporarily store the row and column addresses, respectively, and allow them to be input into the memory module separately through memory address multiplexing.

Why is memory address multiplexing important in DRAM?

Memory address multiplexing allows the memory module to have fewer external pins than would otherwise be required, thus reducing the pin count and simplifying the design, especially in larger memory systems.

What does the row address strobe (RAS) do in a DRAM system?

The row address strobe (RAS) is used to signal the memory module to latch the row address and begin the read or write cycle. It is an active-low signal, meaning it is enabled by setting it to a low voltage.

How are data pins used in DRAM operations?

Data pins in DRAM are bi-directional and used for both reading and writing data. A single pin is required for data input and output during each read or write cycle.

What happens during a DRAM read cycle?

During a read cycle, the bit lines are pre-charged, the row address is applied, and the row is latched into sense amplifiers. The column address is then presented, the data is selected from the sense amplifiers, and the output is available on the data pin.

What is the significance of the row being refreshed during a read cycle?

Refreshing the row during a read cycle restores the original data in the row, even though the read process partially discharges the capacitors storing the data.

How does a write cycle differ from a read cycle in DRAM?

In a write cycle, after latching the row values into the sense amplifiers, the input data is placed on the data line and a write enable signal is applied. The data is then written into the selected cell through a demultiplexer, and the row is refreshed with the new data.