扇出型面板級封裝到底怎麼封? 一口氣弄懂所有封裝詞彙

Summary

This video script delves into advanced semiconductor packaging techniques, contrasting traditional methods with modern fan-in and fan-out approaches. It explains how fan-out packaging, either at the wafer or panel level, allows for more compact chips suitable for wearables and mobile devices. The script also clarifies industry-specific terms like COWOS and FOPLP, and illustrates the evolution from bulky to miniature packaging, akin to a character's transition from heavy armor to lightweight gear in a comic story.

Takeaways

• 📝 Traditional packaging involves a lengthy process with steps like photolithography, deposition, etching, and CMP to create semiconductor chips.
• 💵 The need for external circuit connections and protection against environmental factors necessitates the creation of a plastic casing around the chip.
• 💲 Advanced packaging techniques like 2.5D, 3D, and Fan In/Out packaging have emerged to meet the demands of smaller electronic devices.
• 💵 Fan In packaging keeps metal balls within the chip boundary, suitable for simpler chips with fewer pins.
• 💲 Fan Out packaging extends metal balls beyond the chip boundary, accommodating more pins for complex, high-end chips.
• 💵 Wafer Level and Panel Level are terms that distinguish the scale and material of the carrier used in advanced packaging processes.
• 💲 The Fan Out Panel Level Packaging (FOPLP) uses a larger glass carrier instead of a silicon wafer, which allows for more chips to be packaged at a lower cost.
• 💵 RDL (Redistribution Layer) is a critical structure in advanced packaging that connects the tiny internal circuits of the chip to the larger pins on the PCB.
• 💲 Semiconductor foundries like TSMC, Samsung, and Intel excel in creating RDL structures due to their experience with semiconductor equipment.
• 💵 The choice between Fan In and Fan Out packaging depends on the number of pins required by the chip's complexity.
• 💲 The transition from traditional packaging to advanced packaging is driven by the need for smaller, more efficient chips suitable for wearable and mobile devices.

Q & A

What is the significance of TSMC's COWOS packaging process in the news?

TSMC's COWOS packaging process is significant because it is driving major chip manufacturers like NVIDIA and AMD to consider alternative packaging methods such as FOPLP for producing AI chips due to full order books.

What does the term 'traditional packaging' refer to in the context of semiconductor manufacturing?

Traditional packaging refers to the older method where a blank wafer is processed to become a semiconductor chip, which then requires additional steps to create external circuit connections and a protective plastic casing before it can be used in electronic devices.

Why is the size of traditionally packaged chips a concern for modern devices?

Traditionally packaged chips are relatively large and suitable for larger devices like TVs and computers. However, with the advent of wearables and mobile devices, there is a need for smaller chips to fit into these compact devices.

What is the difference between Fan-In and Fan-Out packaging?

Fan-In packaging places the metal balls within the chip's boundary, while Fan-Out packaging extends these balls beyond the chip's boundary, allowing for more I/O connections on high-end processing chips.

What is the purpose of the Redistribution Layer (RDL) in advanced packaging?

The Redistribution Layer (RDL) serves as a bridge connecting the tiny internal circuits of the chip with the relatively larger pins on the PCB board. It is created using semiconductor fabrication processes like photolithography, metal deposition, and etching.

Why are companies like TSMC, Samsung, and Intel well-suited for manufacturing RDL structures?

These companies have extensive experience with semiconductor fabrication processes, making them adept at creating high-quality RDL structures with precise metal line processes and other chemical methods.

How does Wafer Level Packaging differ from traditional packaging?

Wafer Level Packaging involves performing packaging on the entire wafer before dicing the individual chips, whereas traditional packaging processes each chip separately after it has been diced from the wafer.

What is the advantage of Panel Level Packaging over Wafer Level Packaging?

Panel Level Packaging uses a larger glass substrate instead of a silicon wafer, which can accommodate more chips at once, thereby reducing packaging costs due to the increased area and the use of less expensive glass material.

Why is the choice between Fan-In and Fan-Out packaging dependent on the chip's I/O requirements?

Fan-In is suitable for simpler chips with fewer I/O connections, while Fan-Out is necessary for high-end processing chips that require thousands of I/O connections, which Fan-In cannot accommodate.

What is the process difference between Fan-In and Fan-Out packaging?

Fan-In is a one-stage process done directly on the wafer, whereas Fan-Out is a two-stage process that involves placing diced chips on a carrier wafer, creating a fan-out area, and then proceeding with the packaging steps.

How does the use of glass as a carrier substrate in Panel Level Packaging affect cost efficiency?

Using glass as a carrier substrate allows for a larger area to accommodate more chips, reducing the cost per chip due to the economies of scale and the lower material cost of glass compared to silicon wafers.