Chapter #2.3 - CMOS process [en]

Summary

This lecture explores the n-well CMOS process, a key method in integrated circuit manufacturing. It builds upon previous topics like photolithography and masking techniques, explaining how CMOS circuits, particularly nMOS and pMOS transistors, are created on silicon substrates. The process uses complementary masks to define active regions, gate formation, and metallization steps, ensuring precise alignment and connectivity. The lecture highlights the significance of CMOS technology in modern circuit design, emphasizing its efficiency and scalability, and concludes by discussing design rules and future practical applications.

Takeaways

• 🔍 The lecture focuses on the n-well CMOS process, an essential technique in integrated circuit manufacturing, particularly for creating complementary MOS (CMOS) circuits.
• 🖼️ CMOS (Complementary Metal-Oxide-Semiconductor) technology is dominant in the IC industry due to its efficiency and the ability to implement logic with both nMOS and pMOS transistors.
• ⚙️ CMOS inverters are created by pairing an nMOS and a pMOS transistor, where the pMOS is connected to the voltage supply (VDD) and the nMOS to the ground, providing complementary logic.
• 🔄 The n-well CMOS process involves starting with a p-type silicon substrate and creating n-well regions for the pMOS transistors, enabling a complementary layout for the circuit.
• 🔬 Oxide layers are crucial in CMOS fabrication, serving various purposes, including gate dielectric, transistor isolation, and mechanical support for interconnects.
• 💡 The n-well is formed through processes like photolithography, ion implantation, and etching, allowing precise definition of active regions on the substrate.
• 🎛️ In CMOS design, self-alignment of the gate oxide ensures accuracy in channel length, which defines the transistor's minimum feature size.
• 🔗 Metallic contacts and interconnects are added through successive layers of metals, using masks and photolithography to connect and route the circuit components.
• 🛡️ A passivation layer, often opaque, is applied to protect the IC from damage and reverse engineering, followed by wire bonding to connect the IC to external pins.
• 🔄 The lecture emphasizes the significance of design rules in CMOS IC design, which abstracts the manufacturing process for efficient circuit layout and simulation.

Q & A

What does CMOS stand for, and why is it important in integrated circuit design?

CMOS stands for Complementary Metal-Oxide-Semiconductor. It is important in integrated circuit design because it uses complementary networks of n-type and p-type transistors, which offer advantages in power efficiency and scalability. CMOS is the dominant technique in the industry for building logic gates and circuits.

What is an 'n-well' in the context of the CMOS process?

An n-well is a region within the p-type substrate where p-type transistors are formed. It provides a substrate for the p-transistors in CMOS circuits. The creation of the n-well is one of the first steps in the CMOS process.

Why is silicon widely used as the base material in CMOS processes?

Silicon is widely used because it allows the growth of silicon dioxide, which plays multiple roles in the CMOS process, such as serving as a gate dielectric, providing isolation between transistors, and supporting interconnects. Silicon's ability to form this stable oxide makes it the ideal material for creating integrated circuits.

What role does photolithography play in the CMOS process?

Photolithography is a crucial step in the CMOS process that allows precise patterning of the different layers of the circuit. A mask is used to expose specific areas of a photosensitive material to light, after which certain areas are etched or doped, creating the features of the circuit.

What are the differences between ion implantation and diffusion doping?

Ion implantation is a more controlled process that allows for precise placement of dopants and creates anisotropic doping profiles. Diffusion doping, on the other hand, is isotropic and less controlled, meaning the dopants spread out in all directions, making it less suitable for precise applications in modern CMOS processes.

What is the purpose of the oxide trench created during the CMOS process?

The oxide trench isolates active regions of the transistors, preventing unwanted electrical interactions between them. This isolation is crucial to avoid parasitic diodes and maintain the integrity of the individual transistors within the circuit.

What is a 'self-aligned' gate in CMOS technology?

A self-aligned gate refers to the process where the gate of the transistor is formed before the source and drain doping steps. The gate itself acts as a mask, ensuring that the channel between the source and drain is perfectly aligned with the gate. This improves the precision and performance of the transistors.

How does the CMOS inverter circuit function?

A CMOS inverter consists of an n-type MOSFET (NMOS) and a p-type MOSFET (PMOS) connected in series. When the input is '1' (high voltage), the NMOS conducts and pulls the output to '0' (low voltage). When the input is '0', the PMOS conducts, pulling the output to '1'. This complementary behavior creates the inversion effect.

Why is the gate oxide thickness critical in the CMOS process?

The gate oxide thickness is critical because it directly affects the capacitance of the gate, which in turn influences the transistor's switching speed and power consumption. A thinner oxide layer allows for faster switching and lower power use, but it must be precisely controlled to avoid leakage and reliability issues.

What is a 'passivation layer' and why is it important?

The passivation layer is the final protective coating applied to an integrated circuit. It protects the circuit from environmental factors such as moisture and contaminants, and prevents damage during handling. In modern chips, passivation layers are often opaque to prevent reverse engineering of the circuit.

How is metallization used to complete the CMOS process?

Metallization involves adding conductive metal layers, such as aluminum, to connect various parts of the transistor (source, drain, gate) to each other and to external circuitry. Multiple metal layers, separated by insulating oxide layers, are often used to create complex interconnections within the chip.

What is the purpose of the 'pad mask' in the CMOS process?

The pad mask defines the areas where metal contacts, or pads, are exposed to allow external connections between the integrated circuit and the package it is placed in. These connections are essential for integrating the chip into larger systems and making it operational in devices.

Outlines

00:00

🔬 Introduction to CMOS Process

This section introduces the CMOS process by briefly reviewing previous discussions on photolithography, epitaxial growth, doping, and etching. It explains how these processes combine to form integrated circuits on a silicon substrate, laying the groundwork for understanding the end-well CMOS process, which dominates modern integrated circuit design due to its efficiency and widespread adoption. The basic structure of a CMOS inverter is explained, highlighting the role of NMOS and PMOS transistors and the complementary design logic behind CMOS circuits.

05:00

🔄 CMOS Manufacturing Process Overview

This paragraph delves into how CMOS circuits are built using complementary masks to simultaneously process NMOS and PMOS transistors. It starts with a P-type substrate where N-wells are created to house the P-type transistors. The complementary nature of the process is highlighted, as each step is done for both NMOS and PMOS transistors using specific masks. The importance of CMOS logic's energy efficiency and its scalability for large-scale manufacturing is emphasized, setting the stage for the detailed manufacturing steps.

10:02

⚙️ Defining Active Zones in the CMOS Process

This section explains the role of the active mask in defining regions where transistors will be formed, such as the drain, channel, and source. The active regions are those where electrons or holes will flow, essentially determining where the electrical connections within the transistor occur. The summary explains how oxide layers and molecules are used to separate these regions and prevent unintended connections, preparing the substrate for the next steps in the transistor formation.

15:04

📏 Gate Formation and Alignment

Here, the script describes how the gate oxide is grown and the importance of its precise thickness, as it affects the gate's capacitance. Polysilicon is deposited to form the conductive gate, with masks defining the channel length. The term 'self-aligned gate' is introduced, explaining how the gate structure ensures proper alignment between the source and drain. This step is crucial for defining the transistor's size and performance, particularly in modern 22-nanometer transistors.

20:05

🔗 Drain, Source, and Doping Alignment

This section covers the creation of the transistor’s drain and source regions using ion implantation. The gate structure acts as a protective barrier, ensuring that the doping is precisely aligned with the channel. The 'self-aligned gate' technique ensures that the transistor’s components are well-positioned without overlap, which is crucial for reliable transistor function. The steps for doping both NMOS and PMOS transistors are discussed, as well as the role of the polysilicon gate in protecting specific regions during this process.

25:07

🔧 Interconnects and Metallization

In this part, the metallization step is explained, where metal layers are added to connect the different parts of the transistors (such as the drain, source, and bulk). A highly conductive material like titanium is used to form ohmic contacts, ensuring efficient current flow between the metal and the semiconductor. Oxide layers are added to provide isolation between the components, and photolithography is applied to remove unwanted metal, leaving only the desired connections.

🔒 Finalizing the CMOS Circuit: Passivation and Packaging

This final section explains the last steps in the CMOS manufacturing process, where additional metal layers are applied to create external connections. A passivation layer is added to protect the integrated circuit from damage and reverse engineering. The script concludes by describing how wire bonding is used to connect the metal contacts to the external pins of the circuit’s package, finalizing the CMOS inverter for use in electronic devices.

Keywords

💡CMOS Process

The CMOS (Complementary Metal-Oxide-Semiconductor) process is the dominant technology for manufacturing integrated circuits (ICs). It involves creating both NMOS (n-type MOSFET) and PMOS (p-type MOSFET) transistors on a single substrate. In the script, the CMOS process is highlighted as the primary method for building circuits due to its efficiency and scalability in producing very large-scale integrated circuits (VLSI).

💡N-Well

The N-Well is a region within a P-type substrate used to house P-type transistors in the CMOS process. It provides the necessary environment for the complementary structure of CMOS circuits. The script discusses the N-Well as an essential part of the process, explaining how it is created and how it supports the P-transistors in the circuit.

💡Photolithography

Photolithography is a process used to transfer patterns onto a substrate by exposing it to light through a mask. It is a critical step in defining various regions of an IC, such as the active zones, gates, and interconnects. The script mentions photolithography as a technique for selectively etching or depositing materials at different stages of the CMOS process.

💡Polysilicon Gate

The polysilicon gate is a conductive layer placed on top of the gate oxide to form the gate terminal of a transistor. This layer plays a key role in controlling the transistor’s operation by acting as an electrode. The script explains how the polysilicon gate is deposited, patterned, and aligned to form the channels of both NMOS and PMOS transistors.

💡Doping

Doping is the process of introducing impurities into a semiconductor to modify its electrical properties, such as creating N-type or P-type regions. In the CMOS process, doping is used to form the source and drain regions of the transistors. The script refers to doping techniques like ion implantation and diffusion to precisely control the characteristics of these regions.

💡Oxide Layer

The oxide layer, often silicon dioxide, serves multiple purposes in the CMOS process, such as insulation, gate dielectric, and protection. The script emphasizes the importance of oxide layers in separating transistors, isolating circuits, and providing a foundation for interconnects.

💡Trench Isolation

Trench isolation refers to the use of oxide-filled trenches to electrically isolate different regions of the chip, particularly between transistors. This prevents leakage currents and parasitic effects between adjacent devices. The script describes how trench isolation is created to separate active regions of transistors in CMOS circuits.

💡Active Region

The active region is where the transistors, including their source, drain, and channel, are located. This is the area where current flows and where the transistor performs its switching action. The script explains how the active regions are defined using masks and photolithography, and how oxide trenches are used to isolate them.

💡Self-Aligned Gate

A self-aligned gate ensures that the gate terminal of a transistor is perfectly aligned with the source and drain, improving performance and reducing overlap capacitance. The script mentions how the polysilicon gate and gate oxide layers serve as a mask during the doping process, ensuring precise alignment of the transistor’s channel with the gate.

💡Ohmic Contact

Ohmic contacts are regions where a metal forms a low-resistance, linear connection to a semiconductor. These contacts are crucial for ensuring efficient current flow between the metal interconnects and the semiconductor regions (e.g., source and drain). The script describes the creation of ohmic contacts using highly conductive metals like titanium to minimize voltage drops.

Highlights

Introduction to CMOS process and review of photolithography, epitaxial growth, doping, ionic implantation, and etching as methods to create integrated circuits on silicon substrates.

Explanation of why CMOS (Complementary Metal-Oxide-Semiconductor) is the dominant process in integrated circuit design, especially over NMOS.

Overview of the CMOS inverter circuit using NMOS and PMOS transistors, demonstrating how complementary networks of transistors implement logic and its complement.

Detailed explanation of the CMOS NAND gate, where the NMOS and PMOS transistors are arranged in series and parallel to create complementary logic.

Introduction to the N-well CMOS process, explaining the creation of an N-well in a P-substrate as a template for manufacturing CMOS circuits.

Importance of silicon oxide in the CMOS process as a dielectric material, trench isolation, and a foundation for interconnects, enhancing circuit performance and reliability.

Step-by-step breakdown of the N-well CMOS process, beginning with the P-substrate, oxide growth, and the formation of the N-well through ionic implantation.

Explanation of self-aligned gates and the precision offered by ionic implantation in aligning the channel, drain, and source regions of the transistor.

The role of the gate oxide in transistor function, where its thickness determines the capacitance and behavior of the transistor gate.

Description of how the gate and source/drain regions are doped in CMOS transistors, and the creation of contacts between metal layers and the semiconductor regions.

Details on the metallization process, including the use of titanium for ohmic contacts and multiple layers of aluminum interconnects to link different parts of the circuit.

Introduction of the passivation layer, its role in protecting the circuit, and the final pad mask step to connect the circuit with external packaging pins.

Brief overview of design rules abstraction, which will be covered in the next lecture, emphasizing how the process is linked to CAD tools like Virtuoso.

The importance of controlling the feature size of transistors in defining the performance of integrated circuits, highlighting the challenges of scaling CMOS technology.

Final remarks on how the CMOS process is well-suited for large-scale manufacturing, with a focus on power efficiency and the scalability of the technology.

Transcripts

hi so in this section we talk about

uh the end well cmos process

so last time we discussed

photolithography

and advanced technique of the mask

exposition

and the time before that we talk about

um

all the different operation that we can

apply

to the mask including

epitaxial growth so growing

something on the substrate and oxide for

example

doping and ionic implant

and etching and we have seen that

combining these three steps

step by step we can create an integrated

circuit

by connecting different layer of

semiconductors and metals and we create

a circuit

on a silicon substrate this way

in this lecture we're going to see the

details

of such a process and we will see a

specific one

the end well cmos process now before

i dive into the subject i'd like to

explain

quickly why we talk about cmos

cmos means complementary mass mass comes

from the transistor mass

and so explain why we explain this

process and why this process is actually

the the main the main one used in this

in the integrated circuit industry

and the reason is uh we will see that in

the next lecture the reason is

[Music]

that the main circuit design technique

is the cmos technique we will see that

there are other types of

circuit that we can that that was used

actually

for example nmos but now the dominating

one

is the cmos uh circuit design technique

and so the cmos

process and in particular the annual

cmos process is dominating so we will

see

uh in this lecture what that is but uh

what is a cmos circuit

so that we're on the same page we can

take the example of

the inverter for example so let's draw a

cmos inverter

it's like that so we have the ground

here

the first transistor is the nmos and the

second transistor is the pmos and the

pmos

is connected to vdd and we create the

cmos inverter by connecting the two

gates together

and we have here the output and here the

input

now the principle of a complementary

mos circuit is that you have

a network of n-transistor implementing

the logic

um and implementing uh yeah

the the network of nmos transistor

implements the logic

and you have a complementary network

of p transistor which implements the

complement of the logic

so for example with the the simple

example of the inverter

if you have the input that is connected

to a one

uh then you will activate the nmos

transistor and you will

drive a zero to the output so a one

gives a zero

and then when uh the the inputs change

from one to zero

the n-mos transistor is deactivated and

so instead of having

a high impedance output

it's the p transistor that is activated

and drives a 1.

and so this is the principle for any

gate designed with the cmos

design technique you will have a network

of transistor

of n transistor implementing the the

logic and you will have a symmetrical

network of transistor

implementing the complementary logic for

example

we can quickly draw a nand gate

cmos nand gate this way so we have two

n transistor in series

and this would be the output and then

you will have

a complementary network of p

transistor and since it's complementary

they are in parallel

so we will see the details of all that

in the next lecture

so yeah so here we have vdd and then we

connect the gates

together for example this way oops

here and so here it's a nand gate and we

can connect

two gates together for example uh this

way and then we get an

end gate so yeah so we will

talk about that in the next lecture here

the

what we are interested in is that we are

going to see how we

manufacture such circuits and so you

have to imagine that

the idea behind a complementary moss

is that we can build the two

networks of transistors using

complementary sets

of masks so we will for each

step of the way we will do the step for

the

n mos and the pmos at the same time

using complementary mask

so we start with a p substrate

here

and and we will see the first step that

we do

is that we create because inside the p

substrate we can

easily create an nmos and then inside

the p substrate we create

what's called n well

and this n well will be uh the

the substrate for the p transistor and

so uh

this is the template to design any uh

any cmos circuit we have a p substrate

an n

well and then we apply all the masks and

all the steps

in a complementary way you will see that

okay and yeah just to finish on that

subject

the the reason why we use cmos is

because of the property of cmos logic

which we will see in the next lecture

and

because the nrcmos process is well

well adapted to very large scale and now

is

i mean we know how to do that well

okay so uh let's start with the process

so we start with a p

substrate on which we can grow uh

oxides so we have already discussed

about that the

the reason we use silicon instead of

other semiconductors

is mainly the ability to grow an oxide

and the oxide will be used

you'll see in every step of the process

because we can use the oxide

as a dielectric for the gate as a

capacitance

we can use it as protective layers we

will use that a lot

we can also use the oxide as isolation

between transistors

for example between the p and the n

transistor between the n well and the p

substrate we can use a

trench isolation we call that field

oxide

and we also use the oxide as foundations

for the interconnect because the

interconnects are

heavy compared to the rest and so we can

isolate the transistors from the

interconnect and

use this isolation as a foundation to

support

the interconnect so really the oxide is

used a lot

in the cmos process

so we start with our substrate on which

we have grown

an oxide and then we apply

our p negative rp

to begin with and we apply the n-well

mask

to create as i said here uh the

substrate for the p

transistor that's the first step to do

so uh

we apply the rp we put the mask on and

then we apply

the light and since it's a negative

rp only the zone that

was exposed is not removed by the

solvent

okay so the zone that was not exposed

that was protected by the mask

is removed by the solvent and

then we can etch the rest of

oxide and we can do a ionic implant

remember that we also

could uh and we can and we did

use uh diffusion doping but diffusion

duping is isotropic

while ionic implant is anisotropic so we

use that

to create the the n-well

which gives its name to the process and

the n-well will be the substrate for the

p-transistor so here we will have

the end transistor here and the

p-transistor here

you'll see how it's all symmetrical here

next step cleaning so we remove the rp

we remove

the oxide and we start the next step

oh i forgot to mention that since we

used ionic implantation instead of

diffusion

we need a reheat to clean the surface

because ionic implantation is a bit

can damage the surface so next step

we grow another layer of oxide

to protect

this time we're going to design the

active zone so you'll see

when when you do the lab

we have to select what are the active

zone and sometimes

students are confused about what is the

active zone

and the mask active that comes that

define this zone

the active region are simply where the

transistors

are going to be positioned on the onto

the substrate

including the drain the channel and the

source

and it's uh the active region also

include the bulk and the tap to the

substrate so the connection the

the the connection to the substrate so

um

the active mask is really where um

electrons are or

holes are going to flow okay you can see

that that way or you can just see that

it's just where the transistor will be

the whole thing

so yeah so we use that for n plus and p

plus region to tap the substrates

p and n and a drain and source

and end the channel so we first

grow an oxide and then we deposit a thin

layer of

these chemicals here these molecules

because you'll see that it will you'll

see that in the next step it will help

in the next step and then we apply of

course

the rp we apply the active

mask and we apply photolithography and

you see here

those are the region all the active

region

in yellow here where we will have a

connection so for example this one here

will be the top

the bulk the connection to the p

substrate here will be the connection to

the end substrate

here we will have the p transistor and

here we will have

the n transistor also note that

the mask represented here are its

cumulative so we have here the n-wall

mask

and on top of it we have the active mask

so once we have selected this zone and

we have applied the light

here we have a positive rp so only the

regions that were not exposed

or removed by the solvent and

and then we can grow in these zones in

the zones that are

left open and protected by the rp by the

resin

we can grow an oxide which will

determine where the transistors and

which

will separate all the transistors and

the all the active zone

they will be separated and that's why we

have included this

molecules here because it will prevent

the growth

of the the oxide where it is

placed and so the result is that we have

here trench

of a big trench of oxide in between each

active zone so that the bulk is

separated from the end transistor uh

and the end transistor is separated from

the p transistor and so on

which prevents parasitic diodes and and

and such um so yeah so now we have to

remove these

molecules we have to remove the rest of

the oxide and we keep only the trench

so now we have our two substrates and we

have our

active zones that are separated by oxide

trench

and we can start to design the

transistors

the first step is to design and to draw

the gates

so the way we do that again we grow an

oxide of the silicon

oxide but this time this oxide

will be used as the gate oxide so

compared to the other steps

where the oxide was simply a protective

layer

this layer will be the the size and the

thickness

of this oxide has to be controlled

because it will

affect the capacity the capacitance of

the gate

uh because it's the gate oxide so we use

a cvd technique or the vpe technique

the same to grow this oxide precisely

and uniformly then we deposit

on top of it we deposit the polysilicon

the conductive

gate using the

poly mask and then we apply drp

and we apply the poly mask so

the poly mask is the mask

here that will define the length

of the channel or the

the length of the gate here these widths

here

represents uh the the size the feature

the minimum feature of the transistor so

when you say

when we say that we have a 22 nanometer

transistors

this 22 nanometer refer to the length of

the channel which itself

in the process refer to um

the width of this trace here

and this is this is the the most

critical

uh part of the process because it

defines the minimum

uh length of the transistor so when

uh so this is what limits actually the

size of the transistors

this step the minimum width that we can

achieve with this pulley including

diffraction and all we discussed in the

previous

lecture okay and since we are designing

an inverter don't forget that

we draw the gate for the end transistor

here

we draw the gate for the p transistor

and

we link them together so the mask

has represented here the the two gates

are linked together

and we do that using the poly layer

and so the mask represents this uh

connection between the two

transistors okay so again

rp photolithography solvent we remove

the drp and we can apply

etching and we only keep

the polysilicon gate now we only have

applied the gate and so the

we only have the polysilicon now we need

to create

the drain and the source uh using uh n

plus um doping for the p

substrate to create the end transistor

and

using p plus doping on the n well to

create the p transistor

so same step we apply an rp we apply

the mask now the interesting thing is

that uh

we use uh in this process the reason we

uh position the gate first is because

during the doping of the drain and the

source

we say that the gate is self-aligned

meaning that the the channel of the

transistor will be

uh well aligned between the drain and

the source there is no

small step in between it's really well

aligned

why because we first put

the oxide then we put the poly

layer and then we used the poly layer

and the oxide

as a protective layer for the doping so

you see for example here we have the

p plus mask and the p plus mask

covers the whole active region for

the p transistor here but the doping of

course

will because it's ionic implant it's

precise

it will not go under the

the gate because it's protected by the

gate oxide and the policy and the

polysilicon

so that's why we say that the gates are

self-aligned

only the region not protected by the

oxide

will will have diffusions that will be

used as drainage source

and so here you see we have two steps

one for

the p plus mask which is used for the p

transistors

and the p tap to the substrate

and then we do the next step the the

same step sorry

for the end transistor and the end tap

to the n1

same thing

now we have our transistors formed

we have our connection to uh the p

substrate and the nwl

for the for the bias of

of the bulk and now

we're almost done we need to connect uh

the drain and the source and

the tap to uh the outside world and

to themselves so we need to do uh

the metallization step meaning we are

going to

connect the different part together we

already have connected

the gates together using the polysilicon

now we need to connect

the two drain together for example and

we need to connect

we need to connect the bulk

so the substrate of the end transistor

to

the ground and the substrate of the p

transistor to vdd

and to connect the two drain together

so the first thing we do we apply um a

thin layer

of titanium for example a highly

conductive metal

to all the diffusion remember when we

talk about

the pn junction i said uh when you

connect

two um semicon doped semiconductor

material together you get a depletion

region and i said

when you do that with a metal and a

semiconductor you

also get a depletion region now

we called an ohmic contact

uh contact between a metal and a

semiconductor

such that the properties of the metal in

the semiconductor

allows the current to go through without

without a non-linear effect let's say

okay so it behave

as a resistor and so this is the goal of

this step we put a highly conductive

metal such that the contact between

the source and the drain and the tap

with the metal that we will put later

is good enough okay and there is no

big drop of uh of voltage and such

okay so we first do that and uh

and then we also add a sin uh here it's

represented here

a thin layer of oxide to prevent the

contact between

of course the gate and the drain and the

source

okay so those two steps are

very important and then after that

we deposit um we grow

silicon oxide on top a thick layer

it will be used to isolate the

transistors

from the rest of the interconnect and it

will also be used to support

mechanically support the interconnect

and once we have that we apply the

contact mask and we will draw holes

inside

inside the oxide to put so here are the

contact

mask you see on top of the drain the

source and the tap

and then we can make the metal

the aluminium in that case

flow inside those holes and apply on the

hole

on the whole wafer on the whole

inverter and so here everything is

connected of course we don't want to

connect

everything so we apply the metal one

mask

on top of it we apply rp

photolithography and then we etch the we

remove the metal that we don't

want such that we only keep the

connection

between the source of the end transistor

and

uh the substrate of and the pset the

contact of the p substrate

so this connection here same between

the uh p transistor and the contact to

the n well

this connection here and the connection

between the two drain of the two

transistors

this connection here and the rest you

see this connection here

are removed and then

we are going to do the same thing for

the second layer of metal and we could

do the same thing for the third and

fourth etc

and apply the mask which represents the

interconnection that represents your

circuit so we first grow

an oxide layer a thick oxide layer which

will isolate

between interconnect layer and

will support the next layer then we

apply a mask

which is a vaya between the two

interconnects

so we there is a hole

okay and then we include the second

layer

of metal the metal

again aluminium okay and then we apply

the metal to mask

to select which zone we want to keep and

which zone we want to

remove and here in our case all the

contacts

to do the inverter are done we don't

need another layer of metal to con

to do an uh interconnect so we only use

metal two

to uh connect uh the power supply

uh so basically we're done here the

inverter is finished

and the and and the transistor is

protected by

uh oxide and we have the power supply

which

are connected to the metal two now we

add

the last connection the last layer sorry

is a passivation layer it's a protective

layer

which can be transparent it used to be

transparent or can be opaque

right now we it's common to see so when

you open up an

integrated circuit you don't see we used

to see the connection the

layers of metals and etc because the

oxide is transparent as well

but now we don't see anything because

passivation are opaque

which prevents reverse engineering which

yes you can do reverse engineering with

microscope

so anyway so we applied this passivation

layer which

protects the integrated circuit

and then we apply a last mask which is

called the pad

mask which will be used to connect

in the package connect the metal to

to the pin of the package okay and so in

between we

use um for example

uh we use it's called wire bonding and

these wires

uh can be gold for example or

yeah gold usually and here so we have

our

integrated circuit inside the package

and it's ready to be shipped

so basically that's it for the annual

cmos

process i hope it was clear

in the next lecture we're going to

discuss the design

rules which

are abstraction of this process and

which we are going to use when we design

integrated circuits for example

in virtuoso in the in the lab