L-4.6: What is Hazard in Pipelining | various types of Hazards | computer Architecture

Summary

In this video, the concept of hazards in pipelining is explained, focusing on the three main types: Data Hazards, Structural Hazards, and Control Hazards. The script provides an in-depth introduction to each type, highlighting their impact on instruction throughput and the challenges they pose in achieving ideal CPI (Clock Cycles Per Instruction). Examples of each hazard, such as 'Read after Write' data hazards and issues caused by branching instructions, are discussed to help viewers understand how these hazards occur and how they affect pipelining. The video is essential for competitive and college-level exams, with solutions for handling these hazards also touched upon.

Takeaways

• 😀 Hazards in Pipelining are critical to understand for competitive and university exams, as they are frequently tested.
• 😀 Pipelining aims for a CPI (Clock Cycles Per Instruction) of 1, but achieving this is challenging due to hazards that cause delays.
• 😀 The three primary types of hazards in pipelining are Data Hazards, Structural Hazards, and Control Hazards.
• 😀 Data Hazards occur when instructions that depend on the same data are executed in parallel, leading to conflicts.
• 😀 The three types of data hazards are Read After Write (RAW), Write After Read (WAR), and Write After Write (WAW).
• 😀 Read After Write (RAW) is the most common data hazard, where an instruction tries to read data before it has been written back by a previous instruction.
• 😀 Structural Hazards occur when multiple instructions try to access the same hardware resource (e.g., memory or registers) simultaneously.
• 😀 Control Hazards occur due to branch instructions that change the program flow, causing delays in instruction fetching.
• 😀 Data hazards are resolved using techniques such as forwarding or stalling the pipeline until the required data is available.
• 😀 Structural hazards can be minimized by ensuring that multiple instructions don't conflict over access to the same resources at the same time.
• 😀 Control hazards can be handled by techniques like branch prediction, which attempts to guess the outcome of a branch and continue fetching instructions.

Q & A

What is the primary goal in pipelining?

The primary goal in pipelining is to achieve a Clock Per Instruction (CPI) of 1, meaning one instruction should be completed every clock cycle.

What are hazards in pipelining?

Hazards in pipelining are problems or delays that prevent the ideal scenario where one instruction is executed per clock cycle, affecting the pipeline’s efficiency.

What are the main types of hazards in pipelining?

The three main types of hazards in pipelining are data hazards, structural hazards, and control hazards.

What is a data hazard in pipelining?

A data hazard occurs when an instruction depends on the result of a previous instruction that hasn't yet been completed, leading to incorrect or delayed execution.

Can you explain the concept of 'Read after Write' (RAW) in data hazards?

Read after Write (RAW) is a type of data hazard where an instruction tries to read a register before the previous instruction has written its result to that register.

What are the other types of data hazards besides Read after Write (RAW)?

Other types of data hazards include Write after Read (WAR), where a write happens before a read, and Write after Write (WAW), where two writes occur to the same register in an incorrect order.

What is a structural hazard in pipelining?

A structural hazard occurs when multiple instructions attempt to use the same resource (such as memory or registers) at the same time, leading to conflicts and delays in execution.

How does a control hazard arise in pipelining?

A control hazard arises due to branch instructions. When a branch alters the flow of instructions, the pipeline may need to flush or discard previously fetched instructions that are no longer needed, leading to delays.

How can branch instructions cause control hazards?

Branch instructions cause control hazards because the pipeline may fetch instructions based on a predicted address, but if the branch condition changes, it causes the pipeline to discard incorrect instructions and fetch the correct ones, causing a delay.

Why is achieving CPI = 1 in pipelining challenging?

Achieving CPI = 1 is challenging because hazards such as data hazards, structural hazards, and control hazards cause delays, preventing one instruction from being completed in each clock cycle.