New Disruptive Microchip Technology and The Secret Plan of Intel
Summary
TLDRTSMC hat kürzlich eine 1,6 Nanometer-Technologie angekündigt. In diesem Video erklärt der Sprecher, wie die neuen Transistoren funktionieren und warum die Industrie nun beiderseitige Wafer verwenden muss. TSMC, der Hauptlieferant von Chips für 90% der Welt, hat seine Technologie von 3 Mikrometern in den 80er Jahren bis zu 1,6 Nanometern weiterentwickelt. Die neuen Transistoren basieren auf einer Noel-Transistorarchitektur und einer innovativen Stromversorgung von der Rückseite, was die Leistungsaufnahme reduzieren und die Dichte der Transistoren erhöhen soll. Diese Entwicklungen sind von entscheidender Bedeutung für die zukünftige Chip-Produktion und -design.
Takeaways
- 🌟 TSMC hat kürzlich eine 1,6 Nanometer Technologie angekündigt, die die Herstellung von Chips revolutionieren könnte.
- 🔍 Die neuen Transistoren verwenden eine Noel Transistorenarchitektur und eine Rückseitenstromversorgung, was eine beispiellose Innovation darstellt.
- 🏭 Fast 90% der weltweiten Chipproduktion stammt von TSMC, die die technologische Fortschritt und den AI-Boom antreibt.
- 📈 TSMC hat seit 1987 Fortschritte in der Technologie gemacht, von 3 Mikrometern bis hin zu den neuen 1,6 Nanometer Technologie.
- 🛠️ Die neuen Gate-All-Around Transistoren (Nanosheet) bieten bis zu 35% Verbrauchsersparnis im Vergleich zu FinFET Technologie.
- 💡 Die Rückseitenstromversorgung ermöglicht es, die Stromleitungen unterhalb des Substrats zu platzieren, was zusätzlichen Platz für Signalrouten auf der Oberseite freigibt.
- 🔩 Die Trennung von Stromversorgung und Signalübertragung bietet größere Freiheit für die elektronische Designautomatisierung und beeinflusst die Herstellungs- und Entwurfsabläufe.
- 🚀 TSMC plant, die Gate-All-Around Transistoren Anfang 2025 in Massenproduktion zu bringen, mit den ersten Anwendungen in iPhones.
- 🤝 Intel ist ebenfalls aktiv in der Entwicklung neuer Transistorenarchitekturen und Stromversorgungstechnologien und will sogar TSMC in der Produktion überholen.
- 💼 Die Wettbewerbslage zwischen TSMC und Intel wird durch die Fähigkeit bestimmt, die Technologie zuerst mit akzeptablem Ertrag und minimalen Kosten zu produzieren.
Q & A
Was ist die Bedeutung der 1,6-Nanometer-Technologie, die TSMC angekündigt hat?
-Die 1,6-Nanometer-Technologie von TSMC markiert einen bedeutenden Fortschritt in der Halbleiterindustrie, da sie eine weitere Miniaturisierung von Transistoren ermöglicht, was zu leistungsfähigeren und energieeffizienteren Chips führt.
Welche zwei großen Innovationen bringt die neue Transistortechnologie mit sich?
-Die neuen Transistoren basieren auf einer neuen Transistorarchitektur und der Rückseiten-Stromversorgung, was eine Trennung von Stromversorgung und Signalübertragung ermöglicht – ein bedeutender Fortschritt in der Chipentwicklung.
Warum ist die Rückseiten-Stromversorgung so wichtig für die Chipindustrie?
-Die Rückseiten-Stromversorgung verlagert die Stromleitungen auf die Rückseite des Wafers, was Platz für eine dichtere und effizientere Signalübertragung auf der Vorderseite schafft und die Komplexität der Verdrahtung reduziert.
Was ist der Unterschied zwischen FinFET- und Gate-All-Around-Transistoren?
-FinFET-Transistoren haben einen dreiseitigen leitenden Kanal, während Gate-All-Around-Transistoren mehrere leitende Schichten übereinander anordnen, wobei das Gate den Kanal vollständig umschließt, was die Energieeffizienz erhöht.
Was ist das Ziel von Intels 20A-Prozessknoten, und warum ist er riskant?
-Intels 20A-Prozessknoten kombiniert die Einführung von Gate-All-Around-Transistoren mit der Rückseiten-Stromversorgung, was ein hohes Risiko birgt, da zwei bedeutende Innovationen gleichzeitig eingeführt werden.
Wie beeinflusst die Rückseiten-Stromversorgung die EDA-Tools (Electronic Design Automation)?
-Die Rückseiten-Stromversorgung gibt EDA-Tools mehr Freiheit bei der Platzierung und Verdrahtung von Transistoren, was den Designprozess optimiert und neue Möglichkeiten für die Chipentwicklung eröffnet.
Warum hat TSMC beschlossen, vorerst auf die neuen High-NA-EUV-Maschinen zu verzichten?
-TSMC hat sich gegen die High-NA-EUV-Maschinen entschieden, weil diese derzeit nicht wirtschaftlich rentabel sind. Die Lithographieprozesse mit diesen Maschinen dauern länger, was die Produktionskosten erhöht.
Wie könnte Intel die Kosten für die neue EUV-Technologie senken?
-Intel plant, die Kosten durch die Verwendung von direkter Selbstorganisation zu senken, einem komplexen Prozess, bei dem spezielle Polymaterialien auf dem Wafer organisiert werden, um die Herstellung effizienter zu gestalten.
Was ist das CFET-Transistorarchitektur, und warum ist sie wichtig für die Zukunft?
-Die CFET-Architektur stapelt zwei Nanosheet-Transistoren vertikal übereinander, was die Chipfläche weiter reduziert und eine höhere Leistungsdichte ermöglicht. Diese Architektur wird als nächster großer Schritt in der Transistorentwicklung angesehen.
Was bedeutet der Begriff 'Moore's Law' in Bezug auf die Chipentwicklung?
-Das Moore'sche Gesetz besagt, dass sich die Anzahl der Transistoren auf einem integrierten Schaltkreis etwa alle zwei Jahre verdoppelt, was zu einer kontinuierlichen Kostenreduktion und Leistungssteigerung führt.
Outlines
😀 TSMC's 1.6 Nanometer Technologie-Einblick
TSMC hat kürzlich eine 1,6 Nanometer Technologie angekündigt. In diesem Video wird erklärt, wie die neuen Transistoren funktionieren und warum ab sofort beide Seiten des Halbleiters verwendet werden müssen. Dies ist ein großer Durchbruch für die Branche. TSMC liefert etwa 90% der weltweiten Chips und hat die technologische Fortschritte sowie den AI-Boom maßgeblich vorangetrieben. Die Entwicklung von 3-Mikron-Technologie begann 1987, und nun wurde eine Technologie angekündigt, die Chips mit 1,6 Nanometer ermöglicht. Die neuen Transistoren beinhalten zwei große Innovationen: eine neue Transistorenarchitektur und die Rückseiten-Stromversorgung. Dies ist ein beispielloser Schritt in der Industrie. Die klassischen Flachtransistoren wurden durch FinFET-Transistoren ersetzt, die eine umschlungene Steuerkanalstruktur bieten und eine bessere Kontrolle ermöglichen. TSMC plant, 2025 mit der Produktion von Gate-All-Around-Transistoren zu beginnen, die als Nanosheet-Transistoren bezeichnet werden. Diese Technologie wird die Energieeffizienz um bis zu 35% steigern.
🔌 Rückseiten-Stromversorgung und ihre Bedeutung
Die Rückseiten-Stromversorgung ist ein bahnbrechender Schritt, da bisher alle Signal- und Stromleitungen von der Vorderseite des Halbleiters stammten. Durch die Verschiebung der Stromleitungen auf die Rückseite wird Platz für Signalrouten auf der Oberseite geschaffen. Dies reduziert die Komplexität der Verkabelung und ermöglicht eine dichtere Platzierung der Transistoren. TSMC plant, 2026 Chips mit N2P- und A16-Technologie zu produzieren, die Rückseiten-Stromversorgung verwenden. Intel ist auch an der Entwicklung solcher Technologien beteiligt und will sogar TSMC in der Produktion überholen. Die Entwicklung dieser Technologien wird nicht nur den Fertigungsprozess, sondern auch den Chip-Designprozess beeinflussen.
🚀 Intels Ambitionen und Risikobewusstsein
Intel hat in den letzten 5 Jahren hinter Samsung und TSMC in der hochmodernen Chipfertigung zurückgefallen, aber nun sieht es die Chance, die neue Transistorenarchitektur und Stromversorgungstechnik in die Produktion zu bringen. Intels Gate-All-Around-Technologie, RibbonFET, und die Rückseiten-Stromversorgung, PowerVia, sollen im 20A-Prozessknoten zusammenkommen. Dies ist ein riskanter Schritt, da zwei Innovationen gleichzeitig eingeführt werden. Intel hat in der Vergangenheit konservativer und TSMC riskanter gewesen, aber diesmal ist die Situation umgekehrt. Intel plant, in den nächsten Jahren fünf Knoten in vier Jahren einzuführen, was in der Branche beispiellos ist. Die 14A-Technologie von Intel, geplant für 2027, wird einen riesigen Wandel im Flow mit sich bringen und die erste Verwendung der neuen hochauflösenden EUV-Lithografiemaschinen von ASML, die Kosten pro Wafer aber erhöhen könnten.
💡 Chip-Ökonomie und zukünftige Technologien
Die Wettbewerbslage zwischen TSMC und Intel kommt auf eine einfache Frage an: Wer kann die Technologie zuerst zu akzeptablen Erträgen und zum minimalen Kosten produzieren. Die Einführung der neuen EUV-Werkzeuge und der notwendigen Anpassungen des Prozesses und des Flows führt zu erhöhten Kosten. TSMC hat sich entschieden, die neuen EUV-Maschinen vorerst nicht zu verwenden, da sie wirtschaftlich nicht rentabel erscheinen. Intel hingegen will kreativ werden und versucht, die Prozesse schneller und kostengünstiger zu gestalten, indem es Direkt-Selbstorganisation verwenden will. Die nächste Technologie nach Gate-All-Around-Architektur ist die CFET-Komplementär-FET-Transistorenarchitektur, die den Transistorenflächenbedarf weiter reduzieren und die zukünftige Entwicklung der Silicon-Chips beeinflussen wird.
Mindmap
Keywords
💡Transistoren
💡FinFET
💡Gate-All-Around (GAA)
💡Backside Power Delivery
💡Moore's Law
💡EUV Lithography
💡ASML
💡Intel 20A
💡CFET (Complementary FET)
💡Chip Economics
Highlights
TSMC宣布了1.6纳米技术,这将对芯片行业产生巨大影响。
目前全球约90%的芯片供应来自TSMC的工厂。
TSMC自1987年开始制造3微米技术,现在宣布了1.6纳米技术。
新型晶体管涉及两大创新:新型晶体管架构和背面供电。
新型晶体管架构将信号和电源互连分离,这是前所未有的。
现代芯片由晶体管组成,这些是微小的电子开关。
随着晶体管尺寸缩小,出现了许多问题,如过度泄漏电流。
FinFET技术通过将通道垂直拉伸来解决这些问题。
FinFET晶体管比平面晶体管更紧凑,允许在相同硅片上集成更多晶体管。
所有尖端芯片现在都是用FinFET技术制造的。
整个行业现在正转向新型环绕栅极晶体管,以进一步缩小晶体管尺寸并降低成本。
TSMC计划在2025年初开始生产环绕栅极晶体管。
环绕栅极晶体管在功率效率上有显著提升,比FinFET技术少消耗高达35%的功率。
TSMC的A16技术将基于环绕栅极晶体管,采用背面供电,这是一项突破性技术。
背面供电将电源线移动到晶圆的背面,为信号布线腾出更多空间。
这种分离电源和信号的概念将为电子设计自动化工具提供更多自由度。
TSMC将在2026年开始生产基于N2P和A16技术的芯片。
英特尔也在进行类似的创新,试图在TSMC之前将新技术投入生产。
英特尔的20A工艺节点将采用环绕栅极技术和背面供电。
英特尔的Arrow Lake将是首个采用新型环绕栅极晶体管和背面供电的CPU。
14A将是英特尔计划使用新型高数值孔径EUV光刻机的第一个工艺节点。
英特尔必须在经济上创新,以使高数值孔径EUV机器变得可行。
英特尔计划使用直接自组装技术来降低缺陷率并提高生产速度。
如果英特尔能够成功实现14A节点,这将是英特尔历史上的一个关键时刻。
在环绕栅极架构之后,所有晶圆厂都将转向下一代晶体管架构,即互补FET晶体管。
CFET结构通过垂直堆叠两个纳米片晶体管来进一步减小晶体管尺寸。
Transcripts
TSMC has just announced 1.6 nanometer technology in this video I will explain how these new
transistors work and why from this moment on we have to use both sides of the wafer and why it is
huge for the industry? let me explain! almost all of the world's chips supply today about 90% of it
comes from TSMC fabs and it Powers technological progress as well as AI boom TSMC started making
three Micron Technology in 1987 and just imagine three Micron is like 3,000 nanometers and just
some days ago they've announced new technology that can enable chips at 1.6 nanometers now these
new transistors involve two big Innovations first of all a Noel transistor architecture and backside
power delivery and this is something that has never happened before a separation of power
interconnect from the signalling and as a chip designer I can tell you it's a big deal for the
entire industry. this is a Mona Lisa no no this is a Rembrandt.. no no no I think it's a Michelangelo
right sculpted in Silicon! but to understand the complete picture we have to start with transistors
first all modern chips are made up of transistors these tiny electrical switches that can be turned
on and off this is what a classical planner transistor looks like this switch is controlled
by the gate and when we apply a certain voltage or more specifically a certain electric fill to
the gate it opens the gate and the current flows from the source to the drain as transistors were
scaled down we shrunk the size of the transistor the size of the channel and here we faced many
problems and excessive leakage current is just one of them and eventually the solution was to
completely change the transistor structure so they took a planar transistor and stretched the channel
up as a vertical fin while in a plannar transistor the conductive channel is only on the surface with
FinFET we have a conductive channel on three sides while the gate is wrapped around it allowing us to
better control it and of course compared to the plannar transistors FinFET transistors are much
more compact so with that we're able to pack much more of them into the same silicon die the first
commercial FinFET devices were introduced by Intel in 2011 when I was still at university
and wow we're going to talk a lot about the competition between TSMC and Intel today because
it's really heating up! so a few years years after the first Intel's FinFET device Samsung
and TSMC started fabricating 16nm and 14nm FinFET chips and since then TSMC has led the evolution
of fin fat nowadays all the cutting edge chips are built with FinFET t however FinFET technology has
already reached its limits in terms of how much we can squeeze it in how much the fin can go up and
how many fins we place in parallel side by side and again huge leakage became a problem here so
to further shrink the transistors and drive down the costs the whole industry is now moving towards
the new gate-all-around transistors I've talked about this technology for maybe some years now but
now it's finally moving to mass production TSMC calls their Gate-All-Around transistors Nanosheet
transistors but basically it's the same thing just a different name TSMC plans to begin the
production of gate all around transistors in the beginning of 2025 with the first ones to appear in
iPhones now how does a gate all around transistor actually work basically they took the FinFET
structure and turned it horizontally placing several of these sheets on top of each other so
that we can multiply the number of fins vertically and the best part about it that now the gate is
completely wrapped around the channel the biggest gain with this technology is in power efficiency
gate all around transistors consume up to 35% less power compared to FinFET technology now
just a few days ago tsmc debuted A16 technology on their road map where a stands for Angstrom and
as we discussed in the previous videos this has nothing to do with the real dimensions in the chip
and now we are coming to the most interesting part so tsmc's A16 technology will be based on GAA or
so-called Nanosheets transistors with one very interesting twist backside power delivery and this
is really groundbreaking and yes Intel is doing kind of the same thing and we also will talk about
this later in the video but now let's understand what is this backside power delivery and why it's
so crucial? ever since Robert Noyce made the first integrated circuit everything has been located
on the top on the front side of the wafer with all this signal interconnect and power delivery
coming from the front side so this backside power delivery is quite a huge change because we will
move all the power line so power mesh underneath the substrate to free additional space for the
signal routing on top you know when it comes to Modern chips there are billions and billions of
transistors that are interconnected with each other and there are many levels of signal
interconnect coming on top of the transistors and then there is also power mesh power network on
the top you can imagine it as a network of power and ground lines that distribute power across the
semiconductor chip and provides the power supply to transistors now imagine if we can move all
this power to the back side of the wafer this will reduce the complexity of the wiring interconnect
a lot letting us to place and route transistors much more densely so closer to each other and also
reduce the congestion problems and of course this concept of separating power from the signal will
give much more freedom to EDA electronic design automation tools which are used at this stage and
this means this change will affect not only the manufacturing flow but also the chip design flow
itself and this will require a lot of learning from our side when it comes to power mesh and
the heat distribution on the chip for example tsmc will start producing chips based on N2P and A16
technology which is its version with a backside power delivery in 2026 so I'm really looking look
forward to see how it goes and as mentioned tsmc is not the only company working on this Innovation
Intel is doing the same thing actually Intel wants to be the first even ahead of tsmc to bring the
new transistor technology and power delivery tech into production but before we talk about
Intel's strategy and associated costs and risks did you know that the advanced gate all around and
FinFET transistor architectures would not have been possible without ASM's equipment and process
technology the process of building the most advanced silicon chips nowadays includes thousands
of steps and the most critical among them are lithography etching and deposition because these
are repeated over and over again as transistors are being built on top of the wafer as we scale
transistors down we need to deposed even thinner layers and very precise deposition techniques like
Atomic Layer Deposition (ALD) are essential here Atomic layer deposition is a special technique
that allows to deposit different materials in the wafer atom by atom and with that we can evenly
build very thin layers that are just one atom thick can you imagine that and to do that the most
advanced semiconductor faps like tsmc and Intel use Atomic layer deposition machines from ASM
and I'm very excited that ASM is sponsoring this part of the video ASM is a Dutch semiconductor
equipment manufacturing company and they are one of the pioneers of Al technology with a 55% global
market share in this sector they definitely deserve credit for their contribution into the
continuation of Moore's law because without their machines the advanced FinFET and gate all around
architectures would not have been possible and of course in the future when the next transistor
architecture so-called CFET architecture will become commercially available and this will
clearly stimulate the demand for the ALD equipment from ASM even more you can learn more about ASM
and their products through the link below thank you ASM for sponsoring this video now I want to
spend some time talking about Intel's ambitions because there some very interesting aspects to
this story as you may know for the last 5 years Intel has lagged behind Samsung and tsmc uh in the
advanced chip manufacturing but now this is their chance this is their moonshot to be the first
even ahead of tsmc to bring the new transistor architecture and power delivery into production
for Intel gate all around technology is coming to together with their backside power delivery in
the 20A process node and don't get confused with the terminology because each fab has its own name
for gate round Intel calls it RibbonFET but it's kind of the same thing and now they're putting
the final touches on it and this 20A node we have to watch because it's going to be very important
for Intel and I personally think it's a super risky move for INT to introduce two innovations
at once because you typically want to introduce it one by one to understand where the problems
are coming from but you know introducing two technologies at once is clearly Intel going all
in! and I see a lot of risk here because you know probabilities multiply let me know what you think
in the comments and what's so interesting that in the past Intel used to be the conservative one and
TSMC see was risky but this time it's completely the other way around we also announced that we're
going to get five nodes in four years we're going to do something unheard of in the industry to
return Intel to process technology leadership and while we're not finished today we see the end is
soon in front of us on that journey and Intel 7 shipping and ramping in volume Intel 4 with our
core Ultra launch shipping and ramping and volume Intel 3 is production certified and we'll be with
our server products launching in the first half of the Year going into volume production so with
this we've gone on an incredible journey but then it continues into what we call the angstrom era
and for this Intel 20a and Intel 18a the adoption of ribbon FET a new transistor structure of power
via power delivery technology but this time they really have to deliver Arrow Lake will be
the first Intel CPU to feature their first ribbon fat transistors and backside power delivery which
Intel calls power via and as we just discussed before the idea is the same the power will be
placed under transistors on the back side of the wafer this is all cool but let's be honest from
the entire Intel's road map the most interesting note is 14A a because this is going to be the most
pivotal moment for the Intel Foundry to remind you it's planned for 2027 and I'm really really
curious to see how it goes for Intel because it involves one huge update to the flow one huge and
very expensive elephant in the room 14A will be the first process note where intel is planning on
using the new high numerical aperture EUV lithography machine from ASML one of this
reportedly costs about $380 million and this comes with a lot of risks a part of the risks associated
with the adoption of the new tooling and the updates required to the flow the second risks is
economics which haven't worked so far the reason why Intel is switching to this machine is that
it will allow them to print even finer transistor features EUV lithography machines can print lines
of up to 13 nanometers in width at Advanced nodes beyond 3nm traditional EUV lithography machines
will reach its limit and it will require chip makers to move to euv multi-patterning and this
is complex and expensive and that's by the way how tsmc is planning on achieving N2 and N 1.6 noes
multi-patterning is a technique which often used to overcome the limitations of what is possible
with lithography I've talked about it in the video about the Chinese Chips it involves several layers
of masking and several wafe exposures to pattern a single transistor feature and these new machines
can enable resolutions up to 8nm and with that enable more advanced process nodes and Intel
will be the first fab to adapt these new EUV machines in their flow now when we talk about
how Chip Economics work and by the way it's a super interesting topic and I want to make a
separate video about it if you don't want to miss it subscribe to the channel according to Moore's
law the number of transistors on an integrated circuit roughly doubles every two years and many
people misunderstand this law and think that it's just about a transistor side or the density but
it's actually about the economics it's about transistors getting cheaper and cheaper so now
when we consider the competition between tsmc and Intel ... the clash of two giants it comes
down to just one simple question who can produce it first at decent yield and the most important at
the minimum cost and here they not only have the pressure of time but also the cost pressure and
so far considering the cost of the new EUV tools and the process adaptation and flow adaptation
required it turns out that high NA EUV machines are simply not economically viable as the price
per wafer in this case will be simply too high and according to tsmc that's why they are passing
on this machine for now I was reading another day that the reason why the price per wafer appears to
be too high because at the moment the lithography process with this new machine takes more time
per wafer and this means the fab can process less wafer per day and this limiting the fab
throughput and of course is driving up the costs to make economics to work Intel must get creative
here and it seems they have some ideas how to get around this and make it faster and cheaper their
intention is to use direct self assembly and this is very complex process and to be honest I don't
understand it fully because there is a lot of very complex chemistry involved the idea is that you
cover the wafer with a special poly material and then bake it for an hour or so and when it's baked
these materials self-organize themselves into tiny lines and according to some research which was
previously done on this we can use EUV machines to help to guide the way it's organized on the wafer
but the main problem is this this approach was in the research phase for a decade or so and it
wasn't adapted because the defect rate was just too high but I'm really rooting for Intel here
because for everything they did for the industry I really want them to make it to work you know
but by now you're already aware of all the different Innovations Intel is trying to pull
together at once over the next couple of years and how high the risks are but if they manage to
make it to work especially the 14A node this will be the pivotal moment in the history of
Intel and this will surely help their stock to recover this video is already getting quite long
but just a couple of words what is coming on next following High NA EUV machines we will eventually
get to the hyper NA EUV machines let me know if you want a video about this one in the comments
after gate all around architecture all the fabs will be moving to the next transistor
architecture so-called CFET complimentary FET transistor and this one will help us to further
reduce the footprint and I truly believe in the vertical future of transistors the idea of CFET
is to fold two nanosheet transistors on top of each other vertically to build a CFET structure
intel was the first company back in 2020 to make CFET to work stacking NMOS transistor on top of
PMOS in this way they build this simplest logic circuit you can imagine a CFET inverter when
input is applied to such a circuit its output is a logical inversion of the input so if we have one
at the input we get zero at the output and the other way around and a funny fact that already
back then they had to use the backside power delivery here and the reason is that when we
stack devices the complexity of the interconnect on top just explodes so it's clear that vertical
transistors together with the backside power delivery is the future of transistors
and the future of silicon chips I hope you enjoyed this episode and if you loved it please
share this video with your friends colleagues and on social media I see all your reposts and
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thank you so much for watching guys I wish you a beautiful day and see you in the next episode ciao
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