N bit Multiplier in Verilog (with code)| Verilog Project | Xilinx Vivado | Electronics Project
Summary
TLDRIn this wavelog project, Arjun Narula introduces an n-bit multiplier with a binary to BCD converter. The video demonstrates creating an n-bit multiplier using the shift and add algorithm, converting the binary result to BCD with the double-dabble method. The process is illustrated with a flowchart and Verilog code, showcasing the multiplication of two eight-bit numbers and the conversion of the result to a 16-bit BCD. Test benches are included to verify the functionality with examples, and resources for further learning are provided in the description.
Takeaways
- 😀 The video is a tutorial by Arjun Narula on creating an n-bit multiplier with a binary to BCD converter.
- 📈 The project involves building an n-bit multiplier using the shift and add algorithm, with the result being in binary form.
- 🔄 The binary result is then converted to BCD (Binary-Coded Decimal) using the double-dabble algorithm.
- 📑 The video script provides a step-by-step explanation of converting a binary number to BCD, using the number 151 as an example.
- 💡 A key statement for the double-dabble algorithm is provided: if the number is greater than four, add three and shift; otherwise, just shift.
- 🛠️ The flowchart of the problem is discussed, detailing the process from reset to multiplication and BCD conversion.
- 🔢 The script mentions a parameterized n-bit multiplier, where 'n' can be any value, with an example using n as 8 bits.
- 📝 The Verilog code for the project is available in the video description, and the video includes a test bench for verification.
- 🔄 The multiplication process involves shifting and adding, with specific checks for when to add three during the double-dabble algorithm.
- 📊 The video demonstrates the simulation results for multiplying 26 by 13 and 13 by 13, showing the output in both binary and BCD.
- 👏 The video ends with a call to like, share, and subscribe to the channel, and acknowledges the contribution of Mayank Goel in the project.
- 📚 The video description includes book recommendations for learning Verilog, with links provided for purchase.
Q & A
What is the main topic of the video by Arjun Narula?
-The main topic of the video is an n-bit multiplier project with a binary to BCD converter.
What is the algorithm used for multiplication in the project?
-The project uses the shift and add algorithm for multiplication.
How is the binary result of the multiplication converted to BCD form?
-The binary result is converted to BCD using the double-dabble algorithm.
What is the significance of the 'double-dabble' algorithm in BCD conversion?
-The 'double-dabble' algorithm is used to adjust the BCD digits when they are greater than 4, by adding 3 and shifting the digits.
What is the purpose of the 'reset' variable in the flowchart?
-The 'reset' variable is used to reset the clock and the input when set to 1, allowing for a fresh start of the multiplication process.
How does the 'start' variable affect the flow of the multiplication process?
-When the 'start' variable is 0, it stores the values of a and b, sets the bits, and initializes the output to zero. If 'start' is 1, it checks the zeroth bit of b and proceeds with the multiplication process.
What is the maximum output size in bits for the multiplication of two eight-bit numbers?
-The maximum output size for the multiplication of two eight-bit numbers is 16 bits.
How is the output of the multiplication divided for BCD conversion?
-The output is divided into parts of three bits each, which are then processed for BCD conversion.
What is the role of the 'bit' variable in the multiplication process?
-The 'bit' variable is used to keep track of the number of bits left to process in the multiplication, and it is decreased by one with each iteration.
How are the test inputs applied in the test bench of the Verilog code?
-The test inputs are applied by initializing the multiplier and using a forever loop to create a clock signal, followed by the test inputs for multiplication, such as multiplying 26 and 30 in decimal.
What is the final step in the BCD conversion process as described in the video?
-The final step in the BCD conversion process is to display the output in both binary and BCD form, ensuring the correct representation of the multiplication result.
Outlines
📚 Introduction to N-Bit Multiplier with Binary to BCD Conversion
Arjun Narula introduces a new wavelog project focusing on an N-bit multiplier with a binary to BCD converter. He emphasizes the importance of subscribing to the channel for more content. The project involves creating an N-bit multiplier using a shift and add algorithm, with the binary result being converted to BCD using the double-dabble method. The script explains the theoretical and practical differences in converting binary numbers to BCD, highlighting the double-dabble algorithm's process of adding three and shifting when the number is greater than four. A flowchart is mentioned as a visual guide for the process, which includes initializing variables, performing the multiplication, and converting the output to BCD.
🔍 Detailed Explanation of Verilog Code for N-Bit Multiplier
The script delves into the Verilog code for the N-bit multiplier, parameterized for an 8-bit scenario but applicable to any N-bit value. It explains the output requirements for the multiplication, which can be up to 16 bits for two 8-bit numbers. The BCD conversion process is described as tricky, involving dividing the output into parts of three, adding, multiplying, and subtracting to align with the BCD format. The script outlines the steps in the Verilog code, including initializing registers, handling the reset condition, and performing the multiplication and BCD conversion. A test bench is also discussed, with test inputs to multiply 26 by 30 and 13 by 13, demonstrating the correctness of the implementation. The video concludes with observations on the finished signal and a call to action for viewers to like, share, and comment on the video, as well as a mention of resources for learning Verilog and a thank you note to a contributor.
Mindmap
Keywords
💡Wavelog Project
💡n-bit Multiplier
💡Binary to BCD Converter
💡Shift-and Algorithm
💡Double-Double Method
💡Verilog
💡Flowchart
💡Test Bench
💡BCD
💡Reset
💡Start Signal
Highlights
Introduction of an n-bit multiplier project with binary to BCD conversion.
Encouragement for new subscribers to the channel.
Explanation of using shift and add algorithm for multiplication.
Conversion of binary result to BCD using the double-dabble method.
Theoretical simplicity versus practical complexity in BCD conversion.
Step-by-step guide through the double-dabble algorithm.
Flowchart overview of the n-bit multiplier process.
Reset functionality and its role in the multiplier's operation.
Initialization of output and variable settings for multiplication.
Multiplication process including bit shifting and adding.
Adaptation of the double-dabble algorithm for BCD conversion in Verilog.
Parameterization of n for an n-bit multiplier, with n set to 8 for demonstration.
Division of output into parts for BCD conversion.
Register creation and continuous assignments in Verilog code.
Case statement implementation for the start condition in Verilog.
Multiplication completion check and BCD conversion process.
Test bench setup for verifying the multiplier's functionality.
Simulation results for decimal multiplication examples.
Observations on the 'finished' signal indicating completion of multiplication.
Acknowledgment of contributions and resources provided for further learning.
Closing remarks and call to action for likes, shares, and comments.
Transcripts
hello everyone welcome back to the channel i'm arjun narula
and i'm back with another wavelog project which is n-bit multiplier with binary to bcd converter
so before getting started first of all i like to point out one thing which is that 99 of you have
still not subscribed to the channel so if you are new to the channel please consider subscribing it
motivates us to bring out more such content so now let's get started so what we'll do is that will
create an n-bit multiplier of two numbers it will multiply using shift and algorithm and finally the
answer which would be in binary form would be converted to a bcd using double double method
in the end the output will be displayed in both binary and bcd form so let us see how
can we convert a binary number to a pct form we have a number 151 which in binary is represented
as this now if this number we had to convert in bcd in theory it was a pretty easy task right
we would have assigned just three nibbles and the lower nibble would have gotten the number one
the middle number middle bill would have gotten the number five and the highest number would
have gotten the number one so this was this easy but in reality in computers this does not happen
so what happens let us see so for the double double algorithm i'll just give you a one
statement which will solve the entire thing for you which is if the number is greater than four
you add three and shift otherwise you shift right so now the number is zero so you simply shift here
we have shifted again the number is one you simply shift again we simply shift now the number has
become nine so what we do is we add three we add what do we add three zero one one now once we have
added we again shift again we add three now we again shift again we add three now we again shift
so this way when we reach to the answer the answer is this only what we had written in theory right
so now let us look at the flowchart of the problem so first of all how we'll go is that we'll start
we'll say that if reset is 1 then we'll reset the clock and the input now if reset is 0
then we'll start and we'll see if start is 0 we have a variable start if it's 0 then we
store the values of a and b set the bits and initialize the output with zero if start is
one then we'll check b zero which is the zeroth bit if it is zero then we'll simply shift right
so in the simple multiplication which we saw earlier if it was 0 we simply added
a placeholder right so we'll simply shift if it is 1 then we'll add the multiplier
again so that will be the same thing right we'll add the multiplier right and then shift right
next we'll reduce uh will uh left shift by one will reduce the bits by one and finally we'll
convert the output to the bcd right so now let us get started with the verilog co here we have
parameterized n as 8. now what i need you to understand is that we have made a generalized
n-bit multiplier and here n could be anything 8 16 32 64 128 but for the sake of understanding i
have here taken n as it right so now the output of the multiplication of two eight bit numbers
could maximum be 16 bits right so here the output is of 16 bits if we put n here right
now for the bcd output this part is a bit tricky what we have done is we have divided
that output into parts of three then added one multiplied four and eventually subtracted one
right that this one subtraction is because it is from zero to that number right so if it we
have 16 bits it is 0 to 15 right so now what we do is we declare the inputs we create the reference
registers here we have we are doing nothing just creating the registers right standard theory
next we have the continuous assignments next we have now if you remember the flowchart now we have
the reset now if the reset is one we reset the clock if the reset is zero then we start right
so now we have the case statement with start now if start is zero what we do what we'll do is we
store the values in a and b we'll set the bits and we initialize all the outputs as 0 right so now
if start is 1 right what we do is shift on our multiplication so what we what we are doing is
that a in register is getting shifted to right so that the next bit could be multiplied and b
is getting shifted to the left for the place of the placeholders right here bits is a variable
which is getting decreased by one now if bit gets to zero then the multiplication is completed
right and now here what we are doing is that we are checking the values by hard code
that if whether we need to add three or not right so if the number particular number is
between this range then we'll have to add three or not right so this is what we are doing is
when we use the double double algorithm right
next we have the test bench what we are doing is here we have declared the inputs and outputs
simply initializing the multiplier here we have created clock using forever loop next we have
the test inputs so now we have two test inputs first first one is we'll multiply 26 and 30 in
decimal which is written in decimal then we'll multiply 13 and 13. now let us see the results
so this is the simulation which we'll be looking at so first of all we multiply 26 with 13 right
so as soon as the finished signal gets high here finished signal gets high so we get
the answer as 780 right now to see the 780 in bcd what we do is so first four numbers right
so this is actually a 16 bit bcd right so first four number here i just cross out them
next four will represent 7 next 4 represent
8 and the last 4 represent 0 hence the answer we have got is 780 right in the similar way 13 to
13 multiplication is also correct right next we have some of the observations the out represents
the value of the multiplication value one when finished signal gets to the one right here we
discussed it as soon as the finished signal gets the one our multiplication is completed
right then we have this simple things which we have already uh you know discussed this marks
the end of the video if you have reached till here please do consider to like share the video
here i would also like to thank may goel who has put an immense effort in this project
and has written the code in very long you can find the verilog code in the description
and do write your queries in the comment section also if you are wondering which
book should you buy to study verilog i have written two books in the description
if you want to buy please do consider buying from the link it really helps the channel thank you
foreign
تصفح المزيد من مقاطع الفيديو ذات الصلة
VHDL code for 4 bit ALU and Realization on FPGA development Board
79. OCR A Level (H046-H446) SLR13 - 1.4 Floating point binary part 1 - Overview
Moore Machine Verilog Implementation on Xilinx: ISE D Suite | Digital Design
Linear Congruential Generator Method | Random Numbers
Exploring How Computers Work
Introduction to Data Encryption Standard (DES)
5.0 / 5 (0 votes)