Direct Memory Mapping – Hardware Implementation

Summary

This video explains the concept of Direct Memory Mapping (DMM) in cache memory systems, starting with its basics and leading to its hardware implementation. The speaker describes how physical addresses are divided into tag bits, line numbers, and block offsets, and how multiplexers and comparators are used to match tag bits with cache lines. Through an example, the process of calculating hit latency is demonstrated. The session concludes by discussing the limitations of DMM, focusing on the problem of conflict misses when multiple blocks map to the same cache line, leading to inefficient memory usage.

Takeaways

• 😀 Direct memory mapping (DMM) divides the physical address into tag bits, line number bits, and block offset bits to determine cache locations.
• 😀 The tag directory stores the tag bits associated with each cache line and plays a crucial role in determining whether a memory access is a hit or miss.
• 😀 Cache hits occur when the tag bits from the generated physical address match the corresponding tag bits in the cache line.
• 😀 Cache misses happen when the tag bits do not match, leading to a lookup or retrieval from the main memory.
• 😀 Hardware components involved in DMM include multiplexers to select tag bits from cache lines and a comparator to compare these tag bits.
• 😀 The comparator used for tag comparison is often an XNOR gate, which outputs 1 when the inputs match, indicating a cache hit.
• 😀 The hit latency is the total time taken by the multiplexers and comparator to determine whether it’s a cache hit or miss.
• 😀 An example calculation of hit latency shows that with 11 tag bits and a comparator delay of 8 ns per bit, the total hit latency is 88 ns.
• 😀 Direct memory mapping can be inefficient due to conflict misses, where multiple blocks map to the same cache line, causing unnecessary evictions.
• 😀 Conflict misses occur when different memory blocks repeatedly map to the same cache line, even when other lines are empty, resulting in cache inefficiency.
• 😀 Despite its simplicity, direct memory mapping can cause performance issues in systems with frequent conflict misses, highlighting its limitations.

Q & A

What is direct memory mapping in computer architecture?

Direct memory mapping is a technique where memory blocks from the main memory are mapped directly to cache lines in the cache memory. The physical address is divided into tag bits, line number bits, and block offset bits, which are used to locate data in the cache.

What is the role of tag bits in direct memory mapping?

Tag bits in direct memory mapping are used to identify which memory block is stored in a specific cache line. The processor compares the generated tag bits from the physical address with the stored tag bits in the cache’s tag directory to determine if the data is a hit or miss.

What are the main components used to compare the tag bits in direct memory mapping?

The two main components used to compare tag bits are multiplexers and comparators. The multiplexers select the tag bits associated with each cache line, and the comparator checks if the selected tag bits match the tag bits in the physical address.

How are the multiplexer and comparator configured in the hardware for direct memory mapping?

Multiplexers are configured based on the number of cache lines and the number of tag bits. For example, if there are 4 cache lines and 2 tag bits, 2 multiplexers (4:1) would work in parallel. A comparator is then used to check if the tag bits match. The comparator is typically an XNOR gate.

What does a cache hit and cache miss mean in direct memory mapping?

A cache hit occurs when the tag bits of the physical address match the tag bits stored in the cache’s tag directory, meaning the requested data is already in the cache. A cache miss occurs when the tag bits do not match, indicating the requested data is not in the cache and needs to be fetched from main memory.

How is the hit latency calculated in direct memory mapping?

Hit latency is calculated as the time taken by the multiplexer to select the appropriate tag bits and the comparator to check if the tag bits match. The time taken by the multiplexer is generally very small and can be neglected in many cases, while the comparator delay is more significant.

In the example provided, how was the hit latency calculated?

In the example, the main memory size was 2GB, and the cache size was 1MB. The number of tag bits was determined to be 11 (31 bits for the memory address minus 20 bits for the cache). Given that the comparator delay is 8 ns per tag bit, the total hit latency is calculated as 8 ns * 11 = 88 ns.

What is the formula used to map a memory block to a cache line in direct memory mapping?

The formula used to map a memory block to a cache line is: Cache line number = (Block number) mod (Number of cache lines). This formula determines the specific cache line where a memory block will be placed based on the block number.

What are conflict misses, and why do they occur in direct memory mapping?

Conflict misses occur in direct memory mapping when multiple memory blocks map to the same cache line, causing one block to replace another, even if other cache lines are empty. This happens due to the strict mapping between memory blocks and cache lines.

What is the major disadvantage of direct memory mapping?

The major disadvantage of direct memory mapping is the occurrence of conflict misses, where multiple memory blocks that map to the same cache line cause cache evictions, even when there are empty cache lines available. This leads to inefficient cache usage and increased cache misses.